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Problems about signal dependencies in AXI spec

Yu-Hsin

Hi,

In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require the assertion of WLAST", how should I correctly understand this statement?

My understanding by intuition is that "WVALID should be asserted after WLAST was asserted", but it conflicts to my understanding of AXI signal dependency, or should I interpret "Dependencies on the assertion of WVALID" as BVALID signal?

Thanks.

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    WVALID is asserted at any time the AXI master has valid write data on the WDATA bus. WLAST would only be asserted for the final transfer in a write transaction, so all previous transfers in a write transaction before the final "last" write transfer would have WVALID high and WLAST low.

    So your first intuition isn't quite correct, but I agree with your second interpretation that this applies more to the (eventual) assertion of BVALID.

    The actual requirement being described by the + note is that described in the second part of the 6th bullet point above the diagram...

    "The slave must also wait for WLAST to be asserted before asserting BVALID. This wait is because the write
    response, BRESP, must be signaled only after the last data transfer of a write transaction."

    WLAST isn't shown in the dependencies diagram, so this note was added to describe the additional requirement on transitioning TO the BVALID assertion state - you must have completed the final "WLAST" write data transfer (WLAST/WVALID/WREADY all sampled high) before the slave signals a valid write response).

    The diagram probably is correct as the dependency is on WVALID and WLAST being asserted (the final write) before we can move to BVALID asserted, but it could have been described a bit more clearly.

    Hopefully that clears up what the note was trying to describe.

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    WVALID is asserted at any time the AXI master has valid write data on the WDATA bus. WLAST would only be asserted for the final transfer in a write transaction, so all previous transfers in a write transaction before the final "last" write transfer would have WVALID high and WLAST low.

    So your first intuition isn't quite correct, but I agree with your second interpretation that this applies more to the (eventual) assertion of BVALID.

    The actual requirement being described by the + note is that described in the second part of the 6th bullet point above the diagram...

    "The slave must also wait for WLAST to be asserted before asserting BVALID. This wait is because the write
    response, BRESP, must be signaled only after the last data transfer of a write transaction."

    WLAST isn't shown in the dependencies diagram, so this note was added to describe the additional requirement on transitioning TO the BVALID assertion state - you must have completed the final "WLAST" write data transfer (WLAST/WVALID/WREADY all sampled high) before the slave signals a valid write response).

    The diagram probably is correct as the dependency is on WVALID and WLAST being asserted (the final write) before we can move to BVALID asserted, but it could have been described a bit more clearly.

    Hopefully that clears up what the note was trying to describe.

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