Recently, Cadence Design Systems announced a suite of CCIX IP products which includes Controller, PHY and Verification IP. CCIX (pronounced “C6”) is an open coherent multichip standard that allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to acceleration devices including FPGAs, GPUs, network/storage adapters, intelligent networks and custom ASICs.
The Cadence IP products build on top of their silicon proven PCIe Express Gen4 solution to provide the following critical capabilities for CCIX design and integration:
When building a SoC, the new Cadence IP will be integrated with an on-chip interconnect such as the Arm CoreLink CMN-600 Coherent Mesh Network. The CoreLink CMN-600 is a highly scalable and configurable that blends compute, accelerators and IO within the SoC. The combination of IP allows silicon designers to build any number of high performance solutions ranging from a fixed function accelerator to smart network devices to high core counter servers.
Since CCIX leverages PCIe, the same pins, wires and links can be used in systems that support both protocols. This allows system designer the flexibility to connect legacy PCIe devices or take advantage of CCIX’s higher bandwidth, cache coherency and other performance benefits.
Now taking a closer look within a SoC, the simplified block diagram below illustrates how these new on-chip IP components enable CCIX. The example shows a 64 core mesh design with CMN-600 and 4 channels memory channels with CoreLink DMC-620 (Dynamic Memory Controller).
Attached to one of the edge mesh cross point (XP) routers, you will see the PCIe + CCIX components with the CMN-600 and Cadence IP connectivity. On the CMN-600 side, there is a new Coherent Multichip Link (CML) to compliment the standard IO interface (RNI). The CML provides the CCIX protocol layer functionality and converts the on-chip AMBA 5 CHI protocol requests to CCIX. The CMN-600 then connects to the Cadence IP transaction layers through AMBA AXI on the PCIe interface and through the new CXS (CCIX stream interface) on the CCIX interface. The PCIe or CCIX transactions layers send (or receive) the data transfers from a remote device over the high speed SERDES lanes running up to 25Gbps.
Simplified block diagram illustrates how these new on-chip IP components enable CCIX
By leveraging existing PCIe infrastructure, the integration cost and risk of enabling CCIX is reduced dramatically and now with the Cadence IP available to complement the CoreLink CMN-600, a complete CCIX platform is ready and available for SoC designers. Here at Arm, we are looking forward to seeing what new products and performance points are achieved with CCIX and the new IP.
If you would like to find out more about CCIX please check out the following link.
I thought CCIX was pronounced two zero nine?