Workload modeling utilities are a critical component of a System-on-Chip (SoC) performance analysis solution. They are as important as accurate IP models, deep debug and trace instrumentation and visualization of performance analytics.
We recently announced the AMBA ATP (Adaptive Traffic Profiles) specification that describes a sophisticated workload modeling framework to balance complex synthetic workload generation with ease-of-use.
AMBA ATP models the master and slave high-level memory access behavior of systems in a concise, simple, and portable way. Traffic profiles can be used across multiple tools, design and verification environments to assist with the generation of complex SoCs. In use cases, the traffic profiles enable a simpler and faster simulation mechanism that is simultaneously predictable and adaptive.
Following our introductory blog, we present some examples of AMBA ATP adoption and the benefits that Arm and its ecosystem partners deliver.
Cadence's customers use AMBA ATP to validate and verify the performance requirements of their multi-component, AMBA-based interconnect subsystems. Over the past few years, multiple customers have developed complex performance scenarios that replicate the behavior of various IP blocks in their SoCs, thus mitigating the need to deploy IP modeling. Customers run scenarios over either AMBA VIP for Xcelium or third-party simulation, or alternatively, over the AMBA accelerated Verification IP (VIP) for Palladium emulation. Together with the Cadence Interconnect Workbench (IWB), it’s possible to quickly visualize the performance metrics gathered from the designs, and when necessary, easily debug and identify the causes.
Moshik Rubin, Management Group Director, Verification IP, at Cadence Design Systems explains:
“With the introduction of AMBA ATP, this particular flow has become considerably easier for our customers because ATP replaces low-level UVM sequences by setting a small number of high-level parameters when developing performance scenarios”.
Professor Giovanni Stea, Computer Engineering, at the University of Pisa, has been using AMBA ATP with his team in their modeling tools for worst-case performance evaluation of System-on-Chip implementations. Their investigations show that in a system hosting several masters, it is impractical to assume that each master issues transactions irrespective of the network conditions, since software running at the master only progresses when outstanding transactions are completed.
Professor Stea explains:
"The ATP profiles capture these flow-control properties in a realistic way, increasing the realism of our analyses".
AMBA ATP, in conjunction with 100% accurate Arm Cycle Models and performance analysis frameworks, can help SoC architects and designers develop and share accurate system-level virtual prototypes and run modern workloads on complex Arm-powered designs.
These prototypes can simplify IP evaluation and selection, SoC architecture definition, and system-level hardware and software performance optimization.
In future we will provide example platforms that demonstrate AMBA ATP’s powerful yet simple traffic generation capabilities with Arm Cycle Models from Arm and our ecosystem partners available later this year. For more questions please contact Eric Sondhi, Senior Product Manager, Cycle Models, Arm.