Hello,
I am using Xilinx MpSoc Ultrascale+ ZCU102.
I want to generate an interrupt when dividing by zero.I read the Cortex-R5 technical reference manual (infocenter.arm.com/.../index.jspThe system control register C1 has the DZ bit which control the generation of Undefined Instruction exception. My SW is running as a standalone on R5-0.The file xreg_cortexr5.h consists the XREG_CP15_CONTROL (the C1 Register Defines) but the DZ bit is not exist there. When I tried to change this bit by myself (using inline assembler code) according to the ARM Cortex-R5 details mentioned above and handle this with my own function, I got a SW interrupt in every cycle of my application. Why the DZ bit is not appear in xreg_cortexr5.h?Why changing its value cause a SW interrupt?
Is there a different way to generate the divide by zero interrupt?
Thanks!
The code is:
#define REG_C1_DZ_BIT_MASK 0x80000
iReadValue = mfcp(XREG_CP15_SYS_CONTROL); //Read XREG_CP15_SYS_CONTROL iWriteValue = iReadValue | REG_C1_DZ_BIT_MASK; //Set DZ bit to 1 --> generate an Undefined Instruction exception. mtcp(XREG_CP15_SYS_CONTROL, iWriteValue); //Write to XREG_CP15_SYS_CONTROL iReadValue = mfcp(XREG_CP15_SYS_CONTROL); //Read XREG_CP15_SYS_CONTROL
the values are:
iReadValue = 0xe5187d (First read) iWriteValue = 0xed187d iReadValue = 0xed187d (Second read)
Hi Andy,
Thanks for that!
Any help with my question?