I am trying to configure memory attribute for cortex R52 in our SOC which is having integrated L1 I/D Cache and no coherent agent.and having system RAM.
system is having two clusters with two cores each and other masters like DMA reside outside to the core subsystem having having access to the system RAM memory via the system bus.
So my question is Inner share attribute will share the memory b/w cores of same clusters and outer share attribute memory will share the share the memory with all the cores and with other masters like DMA ?
Not every bus master is connected to the caches. Most often only the CPU cores are. Esp. DMA is mostly left out of this. So if you do a DMA operations, you need to flush/invalidate the addresses where you DMA from/to.
Iam interested in this question. It makes sense to do cache maintenance, but what is the effect of switching from inner to outer? or would that have no effect in this configurations?
Hi Reco - in the Cortex-R52, any memory location in a memory region that is configured as either Inner or Outer shareable is treated as non-cacheable from a processor core perspective. This is commented on in section 7.3 ('Level-1 caches') in the Cortex-R52 Technical Reference Manual. There is no hardware coherency between cores in the Cortex-R52, and so in terms of sharing memory locations the behaviour will be system specific: a location will be shared based on any shared system level caching that is included, or at the target memory location.
Hello David. Is it applicable to the MPU regions containing instructions and declared as inner/outer shared, meaning that instructions shared accross multiple cores (like for an OS kernel) can not be cached in the L1 instruction cache?