Inner/Outer Cacheability in Cortex V8-R

I am trying to configure memory attribute for cortex R52 in our SOC  which is having integrated L1 I/D Cache and no coherent agent.and having system RAM.

system is having two clusters with two cores each and other masters like DMA reside outside to the core subsystem having having access to the system RAM memory via the system bus.

So my question is Inner share attribute will share the memory b/w cores of same clusters and outer share attribute memory will share the share the memory with all the cores and with other masters like DMA ?

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