Hi,
In my Cortex-M0 project, there are two program images residing at different memory locations: 0x0000_0000 and 0x0010_0000. Each program has its own vector table. M0 will boot from the program at 0x0010_0000 then switch to the other program (0x0000_0000) at the end.
What is the correct way to switch to the porgram at 0x0000_0000? I'm not sure whether the following instructions are correct or not.
LDR R6, =0x1 ; set R6 to 0x0000_0001 due to Thumb mode
LDR R0, [R6]
MOV SP, R0
LDR R1, [R6, #4]
BX R1
Can someone please point me the right implementation? Thanks a lot.
Note: r6 should be 0, not 1.
It's only necessary to set bit 0 in PC, that is if you're changing PC directly.
So you should load the SP from address 0x00000000 and PC from address 0x00000004.
Bit 0 is already set for all handlers in the vector table, so you do not need to change anything.
ARM recommends using BX to load PC:
movs r0,#0
ldr r1,=SC
str r0,[r1,#VTOR]
ldr r1,[r0]
mov sp,r1
ldr r1,[r0,#4]
bx r1
... but if you need the code to be shorter, I believe the following will work ...
ldmia r0!,{r0,r1}
mov sp,r0
Edit: I've corrected this answer, so it would work for Cortex-M0+. As mentioned below, the Cortex-M0 (without plus), does not have the hardware register VTOR.
Thank you, jensbauer.
There is an issue while compiling this line: "ldr sp,[r0]"
Error: A1875E: Register Rt must be from R0 to R7 in this instruction
The shorter code encounters a different issue at this line: "ldmia r0!, {sp,pc}"
Error: A1874E: Specified register list cannot be loaded or stored in target instruction set
My toolchain is RVDS_4.1_sp1_build713 armcc/armasm/armlink. Do I miss something here?
I think forgot that you're using Cortex-M0 for a while, sorry about that. To fix the ldr sp,[r0], you'll just need to do for instance...
... I believe that should fix it. The shorter version, probably won't be fixable; I guess I got too used to Cortex-M3/Cortex-M4.
Yes I'm using Cortex-M0. So there is no VTOR in the System Control block. This leads to the compiling error of these two lines,,,
According to the documentation, on Cortex-M0, the exception vector table is fixed at address 0x00000000.
However, since a vendor can customize the behaviour of virtually anything, I know of one implementation, which allows you to change it, though; perhaps there are more.
Fortunately, Cortex-M0+ has a VTOR.
Which device in particular are you writing code for ?
Cortex-M0, not Cortex-M0+.