Cycle count for a subroutine on Cortex M33

Dear All,

I am running a led toggle sub-routine in infinite loop for Cortex M33 on MPS2+ FPGA Board, want to calculate cycle count in one iteration.

ToggleLED_Subroutine PROC

                                                 LDR R0, =0x40302000                                                             ;FPGAIO Base Address(0x40302000) + LED_OFFSET(0)
                                                 MOV R2,#3

Loop                                         LDR R1, [R0]
                                                 EOR R1,R1,R2
                                                 STR R1,[R0]
                                                 B Loop
                                      ENDP

Please assist me to do this 

Thanks a lot.

Parents
  • The Arm Architecture does not specify how many cycles each instruction should take to execute. This is implementation defined.

    Some of the M-profile processors (implementations) list instruction cycle timing in the relevant Technical Reference Manual. For example, the Cortex-M3 Technical Reference Manual lists how many cycles each instruction is expected to take (assuming certain criteria, e.g., zero wait-state memory):

    developer.arm.com/.../cortex-m3-instructions

    Also, Cortex-M23 cycle timing information is documented:

    infocenter.arm.com/.../CHDCICDF.html

    For processors like Cortex-M7 and Cortex-M33 it's not so easy to document such information due to timing variation in the processor pipeline.

    As mentioned by 42Bastin Schick, the architecture does provide debug features for profiling, e.g., measuring performance. For example, the Data Watchpoint and Trace Unit (DWT) in Armv7-M and Armv8-M with the Main Extension provides a Cycle Count Register (DWT_CYCCNT) that can be used for profiling how many processor cycles have elapsed for particular sequences of code running on the target.

    If your device doesn't include debug then the built-in SysTick timer, which can be configured to align with the processor's clock frequency, could be used for profiling, e.g., sample the timer at the beginning and the end of the procedures you'd like to profile.

    In terms of simulators, there are a couple of options:

    • Cycle accurate models
      developer.arm.com/.../cycle-models 
    • EDA vendor tools
      It is possible to generate a TARMAC (Trace ARM ACcesses) listing that contains trace information which includes instruction cycle timings.

Reply
  • The Arm Architecture does not specify how many cycles each instruction should take to execute. This is implementation defined.

    Some of the M-profile processors (implementations) list instruction cycle timing in the relevant Technical Reference Manual. For example, the Cortex-M3 Technical Reference Manual lists how many cycles each instruction is expected to take (assuming certain criteria, e.g., zero wait-state memory):

    developer.arm.com/.../cortex-m3-instructions

    Also, Cortex-M23 cycle timing information is documented:

    infocenter.arm.com/.../CHDCICDF.html

    For processors like Cortex-M7 and Cortex-M33 it's not so easy to document such information due to timing variation in the processor pipeline.

    As mentioned by 42Bastin Schick, the architecture does provide debug features for profiling, e.g., measuring performance. For example, the Data Watchpoint and Trace Unit (DWT) in Armv7-M and Armv8-M with the Main Extension provides a Cycle Count Register (DWT_CYCCNT) that can be used for profiling how many processor cycles have elapsed for particular sequences of code running on the target.

    If your device doesn't include debug then the built-in SysTick timer, which can be configured to align with the processor's clock frequency, could be used for profiling, e.g., sample the timer at the beginning and the end of the procedures you'd like to profile.

    In terms of simulators, there are a couple of options:

    • Cycle accurate models
      developer.arm.com/.../cycle-models 
    • EDA vendor tools
      It is possible to generate a TARMAC (Trace ARM ACcesses) listing that contains trace information which includes instruction cycle timings.

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