a53 core have L1, L2 cache and it is used for read/write data between cpu core and ddr memory.
i don't know if other hardware (such as FPGA) write data to ddr memory, how to detect data was modified.
i tested this problem. (use xilinx ZYNQ MPSoC)
1. ARM : write some random data.
2. read data region for caching.
3. FPGA DMA module: transfer these data to DDR memory region by AXI bus.
4. ARM : read transferred data region.
i think read data on step 4 is cached data on step 2, if it couldn't detect ddr data was changed.
but, test result tell me cache is updated. write data/ read data was identical.
of course all read data cache may be removed other data transition, but there is no fault (read/write data was differ) in a long time test.
So my question is DDR data was changed other H/W by data bus(just AXI bus, not CCI), cache controller can detect it ?
or cache controller continuously monitoring DDR memory data which stored in cache?
You already mentioned CCI. So you need to check which parts of the SoC are covered by the CCI.
I mean if dedicated H/W (like DMA engine) write data to DDR through out of CCI,
how to detect change of data and update valid bit on ARM cache controller.
see below picture, Non-coherent master (right side) write data to DDR. this transfer not connected to CCI, so APU (and it's cache controller) couldn't know data was modified.
so if some DDR location was cached, and that data was modified by other H/W outside of CCI,then only method of set valid bit on APU's cache controller is execute cache update instruction (Clean, Invalidate, Zeroing) mannually.(if there are no other unintended cache update)
is this true ?
i think if it is true, the reason of my test was failed is memory location my app want to read is not cached, so app's read instruction issuing caching from memory.
Right, if H/W does not "know" about modifications of RAM, S/W has to take measures.