I've been trying to implement and test a GICv2 driver on a Foundation model present in the tool ARM DS-5 and facing some issues with interrupts.
I've enabled and set pending an interrupt in the GIC distributer and I actually see that is the highest priority pending interrupt in the GIC CPU interface. I confirm that both I and F bit of the PSTATE are not masked.
I don't know why this interrupt is not forward to the CPU. I've looked at my configuration several times and everything seems to be in place. E.g. Global interrupt settings are enabled both in the distributer and the interface, etc, etc.
I've ran out of ideas, can you help me to solve this problem?
Looking forward to hear from you,
Jorge said:E.g. Global interrupt settings are enabled both in the distributer and the interface, etc, etc.
Does this also include enabling the CPU interface? (GIC_ICCICR)
As you can see in the figure:
GICC_CTRL = 0x201
GICC_PMR = 0xF0
GICC_BPR = 3
GICC_IAR= 0x1C (THE HIGHEST PENDING IRQ)
Is there anything missing?
Do you clear GICR->WAKER?
No, because I'm not using GICV3 in legacy mode. Just GICV2.
Is it something that I have to do?
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