This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Can I enable and use D-Cache with disabled MMU?

Dear experts,

I can't find any information whether d-cache could be used in ARMv8-A with disabled MMU. I found smth here -

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka8788.html, but it seems not related to ARMv8-A.

Thank you!

Parents
  • Hi scopichmu,

    The information to answer this conclusively is distributed around the Arm v8-A Architecture manual that can be found here

    Basically, if the MMU is disabled, then this akin to disabling stage 1 address translations, which, according to sec. D5.2.9 'The effects of disabling a stage of address translation' means that data accesses are assigned the Device-nGnRnE memory type (this assumes  HCR_EL2.DC != 1, see text for more on this case).

    This means that data accesses are treated as Device memory accesses and then, taking sec. D4.4.1 'General behavior of the caches', we have the statement :

    ...

    "It is guaranteed that no memory location that does not have a Normal Cacheable attribute is allocated into the cache."

    We can stop there as you are asking only about D$. So as the data memory accesses are seen as being to Device memory, this means that they would not be cached.

    Hope this helps/clarfies things for you.....

    Regards,

    Stuart

Reply
  • Hi scopichmu,

    The information to answer this conclusively is distributed around the Arm v8-A Architecture manual that can be found here

    Basically, if the MMU is disabled, then this akin to disabling stage 1 address translations, which, according to sec. D5.2.9 'The effects of disabling a stage of address translation' means that data accesses are assigned the Device-nGnRnE memory type (this assumes  HCR_EL2.DC != 1, see text for more on this case).

    This means that data accesses are treated as Device memory accesses and then, taking sec. D4.4.1 'General behavior of the caches', we have the statement :

    ...

    "It is guaranteed that no memory location that does not have a Normal Cacheable attribute is allocated into the cache."

    We can stop there as you are asking only about D$. So as the data memory accesses are seen as being to Device memory, this means that they would not be cached.

    Hope this helps/clarfies things for you.....

    Regards,

    Stuart

Children