in arm7tdmi, when FIQ and RIQ occures at same time so how both are executed sequentially,first FIQ and thenIRQ?

hello,

thanks for replay,

suppose now instructions are being executed in user mode,suppos at address :  0x00000108 some instruction is being executed and while it is being executed, IRQ and  FIQ are raised at same time so according to priority FIQ will be handled first and the address of next instruction at 0x0000110 is stored in ti R14_FIQ and cpsr to spsr_FIQ. so at the return from FIQ, r14_FIQ will be stored pc and spsr_FIQ to cpsr,this is what generaly happens,but suppose IRQ raised at same time FIQ raised then after FIQ handeled ,irq is to be handeled so what would be steps to enter to IRQ handeler after return statement of FIQ handeler,(i.e will it go first to user mode and execute one institution at 0x00000110 as per our example or from FIQ handler(FIQ mode) it will go to irq handler(IRQ mode) .

No, it won't go to User mode and execute an introduction before executing the IRQ vector. The restored LR and CPSR will be copied immediately to LR_irq and SPSR_Irq and the IRQ vector will be executed before any further instructions from the interrupted sequence are executed.

Hope this help.

Chris

thanks for replay,

so what i understood is that on return instruction of FIQ handler, R14_FIQ  and SPSR_FIQ will be copied to R14_IRQ and SPSR_IRQ respectively and  and directly IRQ handler will start execution after completion of FIQ  handler.

and at the return instruction in IRQ handler R14_IRQ and SPSR_IRQ will be copied to PC and CPSR  and control will go to interrupted mode and will start execution next instruction from the instruction which was interrupted in interrupted mode.

correct me if i am wrong.

thank you.

That's now quite what I said!

During the return from the FIQ, LR_fiq and SPSR_fiq will be copied to LR and CPSR. Once that return is complete, execution of the IRQ vector will start and LR/CPSR will be copied to LR_irq and SPSR_irq. So, no direct copy, the values will go via the User mode registers.

Chris

thanks for replay,

so it will go to user mode or intercepted mode before going to IRQ mode

but you said

LR_FIQ to LR_ interrupted_mode and SPSR_FIQ to CPSR

but  i think LR_FIQ should be transferred to PC  instead of  LR_ interrupted_mode

and after that no further instruction will be executed in interrupted mode and PC  will be copied to  LR_IRQ and  CPSR will be copied to SPSR_IRQ while going to IRQ handler (IRQ mode).

so correct  me if i am wrong.

the question is that  LR_FIQ should be copied to PC not to LR_of_interrupted_mode  so did i assume right or wrong?

thank you.

Yes, sorry, my typo. Apologies for any confusion. I meant to say:

>During the return from the FIQ, LR_fiq and SPSR_fiq will be copied to PC and CPSR. Once that return is complete, execution of the IRQ vector

>will start and PC/CPSR will be copied to LR_irq and SPSR_irq. So, no direct copy, the values will go via the User mode (or whichever mode was

>interrupted) registers.

Sorry! I hope it's clear now.

I am still interested to know what problem you are trying to solve which needs this kind of detail about exception sequences...

Chris

thank you very much for solving my problem

and sorry for asking you same thing again and again but i wanted to be

quite sure.

actually i am firmware engineer and i have interest in ARM architecture so

i want to learn it literally and then i want to develop my own RTOS based

on ARM platform.so i need clear picture at ARM isa and ARM processor  level

and how it works.

it is just  that i am crazy about ARM.

again thank you,

nirav

Hi,

I am glad we got that clarified.

Also glad to hear of your interest in ARM. I would recommend, though, that you consider developing for a more modern processor tan ARM7TDMI. As far as we are concerned, that is very old technology these days and we would recommend using a more modern processor such as Cortex-M3 (for microcontrollers) or one of the Cortex-A series (for application processors).

Do let us know if there is anything else we can help with.

Best wishes

Chris

thank you sir,

so as you know i will have to start development form scratch with assembly and c langugae  so can you suggest me any cortex-A sires processor development board with which i can get full software tool support and debugging and emulation support at very low level programming.

some known development boards are there but those are good for application programming on top of some kernel but while developing rots i need to do bare-metal coding and need good support of software and debugging and emulation

The Raspberry Pi Model B uses a quad core Cortex-A7 processor. Tools availability is excellent and bare-metal development is well supported and there is a lot of literature about this online.

Chris