I'm using Jlink with openocd to debug ARM926EJ-S and encountered problem when executing SWI command.
Even though I don't set a break point at SWI handler but the CPU breaks at SWI handler automatically. How to remove the break point and make the CPU run continuously after every SWI command ?
Thank you very much.
Oh I know the reason,
OpenOCD manual says that :
Command: arm semihosting
Display status of semihosting, after optionally changing that status.
Semihosting allows for code executing on an ARM target to use the I/O facilities on the host computer i.e. the system where OpenOCD is running. The target application must be linked against a library implementing the ARM semihosting convention that forwards operation requests by using a special SVC instruction that is trapped at the Supervisor Call vector by OpenOCD.
So run command arm semihosting disable to solve the problem.
ARM does not define a specific breakpoint instruction. It can be different in different OSes. On ARM Linux it's usually an UND opcode (e.g. FE DE FF E7) in ARM mode and BKPT (BE BE) in Thumb.
FE DE FF E7
With GCC compilers, you can usually use __builtin_trap() intrinsic to generate a platform-specific breakpoint. Another option is raise(SIGTRAP).
View all questions in Classic processors forum