here is the statement about fixed burst in axi spec.
The byte lanes that are valid are constant for all beats in the burst. However, within those byte lanes, the actual bytes that have WSTRB asserted can differ for each beat in the burst.if byte lanes that are valid are constant for all beats, the WSTRB signal should be same in all beatswhy do the actual bytes that have WSTRB asserted can differ for each beat in the burst?I am confusedThanks!
Yes, the text could have been better worded.
AWADDR and AWSIZE together tell you the data bus byte lanes that CAN be used for the first transfer in a transaction. For an INCR or WRAP burst these byte lanes that CAN be used increment for each transfer in a transaction (assuming the data bus is wider than the width indicated on AWSIZE), but for a FIXED burst type the data bus byte lanes that CAN be used remain constant.
However within the AWSIZE number of byte lanes that CAN be used in each transfer, WSTRB indicates the byte lanes that ARE being used, and this value can change regardless of the AWBURST type.
So if you have a 128-bit data bus, and AWADDR=0x0 and AWSIZE=0x2 (32-bit) and AWLEN=0x3 (4 transfers), for an INCR or WRAP burst the data bus bits that CAN be used are WDATA[31:0], then WDATA[63:32], then WDATA[95:64] and finally WDATA[127:96]. But for a FIXED burst type the data bus bits that CAN be used are WDATA[31:0] for all 4 transfers (FIXED means this does not change).
But for those 4 FIXED transfers you could use any or all of WSTRB[3:0], so you could have WSTRB=0x000F, then 0x000A, then 0x000F then 0x0006 (basically any value in the range 0x0000 to 0x000F).
So a FIXED bursts means that the byte lanes that CAN be used remains constant for each transfer in the transaction, but WSTRB signalling the byte lanes that ARE used within that allowed range can change between transfers.
Hopefully that makes more sense.
Thanks for your detail response.
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