In the current technology scaling paradigm, where Dennard scaling is dead and Moore’s Law is on life support, semiconductor device physics and conductor parasitics are fundamentally limiting microprocessor performance beyond the 5nm process node. As a result, there are two major physical challenges to implementing microprocessors beyond the 5nm technology node:
(i) Saturating standard cell (logic and memory) scaling
(ii) Power delivery with highly resistive copper interconnects. State-of-the-art logic cells cannot be usefully scaled beyond ~5.5 metal tracks (“5.5T”), and exponentially increasing metal resistance is expected to increase on-die voltage drop by 2.2X from 16nm designs to 3nm designs
Buried-power rails (BPRs) – power rails that are “buried” below the BEOL metal stack, usually in-level with the transistor “fins,” themselves – and back-side power delivery (“back-side” is below the transistor substrate) have been proposed to alleviate these design challenges and enable technology scaling beyond the 5nm technology node. The BPR technology can free up resources for dense logic connections that limit modern processor performance, enable further scaling of a standard logic cell by removing the overhead in the area occupied by the power rails, and allow thicker low-resistance power rails that enable lower voltage (IR) drops.
The Devices, Circuits, and Systems group at Arm Research partnered with Imec to evaluate BPRs and back-side power delivery on Arm cores, targeting the 3nm technology node and beyond. In particular, we looked at a Cortex-A53 “LITTLE” core with three variants of power delivery. The first variant demonstrated the classic power delivery network from the front-side of the chip, which followed conventional power delivery design methodologies. Modern microprocessors are incredibly complex and have high levels of intra-design connectivity, which usually strains the amount of wiring resources available in a given area – densely packed transistors and cells require dense logical connectivity. However, enough wiring resources also need be allocated to the power delivery network for reliable and high-performing transistor operation (see Fig. 1 (i)).
Fig. 1 (i). Cross-section of a die (with a 2-fin transistor architecture) with classical signal and power routing. (ii) cross-section with BPRs with front-side power delivery. (iii) cross-section with BPRs and back-side power delivery. Taken from .
Typically, a ~10% voltage drop is margined from the off-chip regulator to the on-chip transistors, and this helps determine the amount of wiring resources that should be allocated for power delivery. Our initial experiments with conventional front-side power delivery in the ~3nm node were not only unable to meet the performance targets (due to placement congestion and wiring congestion), but the power delivery network designs using regular power rails were unable to meet the voltage drop target; at worst, we observed a ~40% voltage drop.
The second variant of power delivery consisted of front-side power delivery, similar to the first variant, but utilized the BPR technology (see Fig. 1 (ii)). These rails ran in parallel in the silicon substrate and were connected up to the front-side power delivery network with tall vias (“buried” vias). This variant had fewer violations that exceeded the voltage drop margin; however, performance had to be traded-off to stay within the voltage drop margin. The improvement in voltage drop observed with front-side power delivery complemented with BPR technology was not as promising as expected. Despite the low-resistance BPRs, front-side power delivery still needed to deliver power through the highly resistive local metal levels, which posed an IR limitation even with BPRs.
The third variant in our work considered back-side power delivery with BPR technology (see Fig. 1 (iii)). The BPRs were connected to the back-side of the chip using miniature Through-Silicon-Vias, called “micro-TSVs” or “µTSVs,”. The power-delivery network was designed completely on the back-side, using just two metal levels for efficient, low-resistance power delivery. That left the front-side wiring resources to be completely utilized for signal routing and optimized for dense connectivity and high performance, decoupling the interconnect design requirement to trade off IR-drop and microprocessor performance. Back-side power delivery was able to improve the voltage drop by up to 90% compared to front-side power delivery and exhibited only a ~1% voltage drop in the best-case scenario without compromising on energy or performance (Fig. 2).
Fig. 2. Energy metric for the three configurations of power delivery (i) Front-side power delivery (FS), (ii) Front-side power delivery with BPR (FS-BPR), and Back-side power-delivery with BPR (BS-BPR). Taken from .
We presented these findings at the 65th International Electron Devices Meeting (IEDM) in December 2019 . These experiments exhibited promising returns from BPR and back-side power delivery. However, there are a number of designs, manufacturing technology, and packaging complexities that need to be researched and resolved before it is possible to fully enable back-side power delivery with BPRs for wide-spread industry adoption. To find out more about our research, read the following paper, or contact Divya Prasad should you have any questions.
Read the paper Contact Divya Prasad
 D. Prasad, et al, “Buried Power Rails and Back-side Power Grids: Arm CPU Power Delivery Network Design Beyond 5nm,” in the 65th International Electron Devices Meeting (IEDM), Dec. 2019.