Solving problems in an SoC is a non-trivial matter - hardware and software bugs can be time consuming to identify and fix. In a market where time to market is vital, any delay can mean the difference between product success or failure.
Traditionally, designers have relied on JTAG – to debug their SoCs and optimize performance.
Fig. 1 JTAG debug with DS-5
Developers face significant challenges as the product moves from the pre-production bench environment to production ramp, as these JTAG and Trace connection headers are rarely available in an end product’s production form factor.
Fig. 2 Debug over functional I/O with DS-5
The recently announced, ARM CoreSight SoC-600 solves this, by implementing the latest ARM debug and trace architecture. The new architecture provides developers with high-throughput trace and in-field debug accessibility over existing functional interfaces.
Fig. 3 ARM CoreSight SoC-600 implements the latest debug architecture
As a result, developers, OEMs and SIPs can now:
Learn more about CoreSight SoC-600 here.
Fig. 4 Illustration of the demo on show at embedded world
At embedded world, we will demonstrate CoreSight SoC-600 trace connectivity over a USB functional interface to ARM DS-5. The platform will consist of an FPGA target with a dual-core ARM Cortex-A53 CPU, CoreSight SoC-600 components and a USB 2.0 device controller. It will run Linux kernel version 4.7, which will consist of the device driver for the CoreSight SoC-600 components and the USB controller. Once connected to the host PC, the processor instruction trace will be captured and DS-5 will then decode and present it for inspection within the trace view. The demonstration will show how the Linux kernel execution history can be analyzed, including STM events generated from a Linux user space application.