The term DAP refers to the Debug Access Port. The DAP usually includes two parts: the Debug Port (DP) and the Access Port (AP).
The DP can be controlled from an external debugger using Arm’s Serial Wire Debug (SWD) protocol or Joint Test Action Group IEEE 1149.1 (JTAG) protocol. The SWD protocol, described in the Arm Debug Interface Architecture Specification (ADI), may implement version 1 or 2 of the protocol. The version 1 of the protocol supports only a single point-to-point connection. The version 2 of the protocol supports Multi-Drop, allowing one debugger to control multiple DAPs on one or more devices at the same time.
One or more APs in a DAP can send debug requests to processors, CoreSight debug and trace components or memory subsystems.
The DAP provides multiple driving ports, all accessible, and controlled through a single external interface port so that it can achieve:
Over the years, the DAP has evolved and is structured differently in different products. Some chip designers may be unclear on selecting the correct DAP for their required usage, especially when they need to support the multi-drop features in SWD version 2. This document introduces various DAPs to help you understand the differences between DAPs and to help you to choose suitable DAPs for your SoCs.
In the early 2000s, Arm released a DAP-Lite product in some legacy processors’ bundles, such as the Cortex-A9 processor bundle. Figure 1 shows the diagram of this legacy DAP-Lite.
Figure 1: The legacy DAP-Lite
The legacy DAP-lite supports Arm Debug Interface (ADI) version 5 and CoreSight Architecture Specification v2.0. It has the following features:
The DAP-Lite, in the previous section, supports only a single AP, while some designs require a multiprocessor debug and trace solution which needs multiple APs. In the past, Arm provided CoreSight Design Kits to address this requirement. These CoreSight Design Kits provide a fixed DAP, shown in figure 2.
Figure 2: the DAP in the CoreSight Design Kits
The DAP in the legacy CoreSight Design Kits supports ADI version 5 and CoreSight Architecture Specification v2.0. As the design of this DAP is fixed, chip designers cannot modify it.
The DAP in the CoreSight Design Kits has the following features:
As the fixed DAP in the legacy CoreSight Design Kits do not allow designers to select the specific APs needed for their system, Arm developed and released CoreSight SoC-400 to address this. SoC-400 provides configurable CoreSight components so that designers can customize the DAP to match their system requirements.
SoC-400 supports ADI version 5 and CoreSight Architecture Specification v2.
SoC-400 allows designers to select the components to build their DAP. A typical DAP built with SoC-400 has a structure similar to the example shown in figure 3, with the following features:
Figure 3: The DAP built with SoC-400
Though SoC-400 allows designers to select APs according to their system requirements, it does not provide a path to access resources behind each AP. Some designers would like on-chip access to debug and trace resources, especially to have a path that other requesters can access Cortex-M processors’ debug and trace resources, which SoC-400 does not support.
SoC-600 was designed to address these requirements. SoC-600 supports ADI version 6 and CoreSight Architecture Specification v3. A typical DAP built with SoC-600 is shown in figure 4.
Figure 4: DAP example built with SoC-600
The main features of this typical example are as following:
Compared to MEM-APs based on CoreSight Architecture Specification v2.0, the MEM-APs in SoC-600 have the following features and functions:
The DAP-Lite 2 provides two versions of DAPs that are compliant with ADI version 6.0. One DAP supports application and real-time processors with AMBA APB4 debug interfaces, and the other DAP supports microcontroller processors with AMBA AHB5 debug interfaces. The DAP-Lite2 is designed for single Arm Cortex-based processors.
The DAP-Lite2 bundle includes:
Figure 5: DAP-Lite2 AR block
Figure 6: DAP-Lite2 M block
In the legacy Cortex-M processors, including Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, and Cortex-M33, a reduced version of DAP is provided. This DAP has removed some functions and features from the full DAP and can only be integrated with a single Cortex-M processor, and does not support multiple processors design. The reduced version DAP in Cortex-M0, Cortex-M0+, Cortex-M7, Cortex-M23 and Cortex-M33 has also integrated an internal AHB-AP. The reduced version DAP in Cortex-M3, and Cortex-M4 has not integrated an AHB-AP, because the processors have an internal AHB-AP. Some main features of the reduced version of DAP are summarized in the following table.
Protocol on the DP
Either JTAG or Serial Wire
Configurable to support if Serial Wire protocol is selected
Serial Wire or both Serial Wire and JTAG
Both Serial Wire and JTAG