If you've watched any sporting event on television lately, you've seen the pressure put on referees and umpires. They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time from a single vantage point. But watching at home on television, we get the luxury of viewing multiple replays of events in question in high-definition super-slow-motion, one frame at a time, and even in reverse. We also get to see many different views of these controversial events, from the front, the back, the side, up close, or far away. Sometimes it seems there must be twenty different cameras at every sporting event.
Wouldn't it be nice if you could apply this same principle to simulation and emulation runs of your ARM® Cortex™-A series processor-based SoC designs? What if you had instant replay from multiple viewing angles in your functional verification toolbox? It turns out that such a technology indeed exists, and it's called "Codelink Replay".
Mentor Graphics' Codelink Replay enables verification engineers to use instant replay from multiple viewing angles to quickly and accurately debug advanced multicore designs like those built using ARM big.LITTLE™ processing technology that marries the high-end performance of the ARM Cortex-A15 MPCore™ with the energy efficient Cortex-A7 MPCore processor.
Multicore SoC Design Verification
Multicore designs present a whole new level of verification challenges. Achieving functional coverage of your IP blocks at the RTL level has become merely a pre-requisite now - as they say "necessary but not sufficient". Welcome to the world of multicore SoC level verification, where you use your design's software as a testbench. After all, since a testbench's role is to mimic the design's target environment, so as to test its functionality, how better to accomplish this than to execute the design's software against its hardware during simulation or emulation?
Some verification teams have already dabbled in this world. Perhaps you've written a handful of tests in C or assembly code, loaded them into memory, initialized your Cortex-A series processors, and executed them. This is indeed the best way to verify multicore SoC level functionality including power optimization management, clocking domain control, bus traffic arbitration schemes, driver-to-peripheral compatibility, and more, as none of these aspects of a design can be appropriately verified at the RTL IP block level.
However, imagine running a software testbench program only to see that the energy efficient Cortex-A7 processor stopped executing code two hours into the simulation. What do you do next? Debugging "software as a testbench" simulation can be daunting. Especially when the software developers say "the software is good", and the hardware designers say "the hardware is fine". Until recently, you could count on weeks to debug these types of failures.
This is where Codelink Replay comes in. It enables you to replay your big.LITTLE simulations and emulations in slow motion or fast forward, while observing many different views including hardware views (waveforms, CPU register values, program counter, call stack, bus transactions, and four-state logic) and software views (memory, source code, decompiled code, variable values, and output) - all remaining in perfect synchrony, whether you're playing forward or backward, single-step, slow-motion, or fast speed. So when your simulation or emulation run fails, just start at that point in time, and replay backwards to the root of the problem. It's non-invasive. It doesn't require any modifications to your design or to your tests.
Debugging big.LITTLE SoC Designs Quickly and Accurately
So if you're under pressure to make fast and accurate decisions when your SoC level tests fail, you can relate to the challenges faced by professional sports referees and umpires. But with Codelink Replay, you can be assured that there are about 20 different electronic "cameras" tracing and logging each core in your Cortex-A15 MPCore and Cortex-A7 processors during simulation, giving you the same instant replay benefit we get when we watch sporting events on television. If you're interested to learn more about this new technology, register for the upcoming web seminar on May 3rd at the URL below, that introduces Codelink Replay, and shows how it supports the entire ARM Cortex family of processors, including the rest of the Cortex-A series processors, and the entire Cortex-R series and Cortex-M series processors.Guest Partner Blogger:Mark Olen is currently a Functional Verification Technologist at Mentor Graphics Corp. He has spent thirty years in semiconductor design verification and manufacturing test, and has authored papers in the areas of intelligent testbench automation, design for test technology, and semiconductor manufacturing test automation. He wrote his first testbench in 1981 at Raytheon, and went on to spend ten years working at Teradyne in the ATE and DFT industries. He became Vice President of Cascade Microtech's thin film wafer probe division, before co-founding Lighthouse Design Automation where graph-based Intelligent Testbench Automation was first successfully applied to semiconductor design verification. Mark graduated from MIT with a BS in EE&CS.