The trend for the electronics industry remains the same as ever; we want chips that are smaller, faster, more efficient. When you look at the trajectory of SoC designs you can see that the cost of integrating IP rises sharply when a node process is changed. For example, at 10nm the IP integration cost is projected to be almost 4 times that of a 28nm process. It is a growing drain of project resource in terms of money and effort needed to properly integrate a system.
In an effort to solve this integration issue, we need to look within the design flow to identify areas where improvements can be made. One of these is IP configuration. IP configurability is evolving due to the growing reoccurrence of highly complex IP that designers are integrating into their SoCs. Add to this the amount of competition in the IP market, where silicon partners are looking for IP that is tailored to their design in order to optimize system performance.
The above graph, provided by SemiCo Research, shows the costs for 1st time effort at each new node with design parameters maxed out. The trend is clear.
As systems become more complex the configurability requirements for certain types of IP becomes exponentially more complex e.g. a system interconnect (CoreLink™ NIC-450) or a debug and trace subsystem (CoreSight™ SoC-400). These IPs can be considered to have an infinite configuration space which brings a new class of problem.
What we need, then, is more Intelligent IP configuration that is based on the system context and configured with awareness of PPA constraints making the downstream IP integration process simplified and highly automated.
Another thing to consider is the highly iterative nature of the IP Integration cycle. Between specification, configuration and integration of components it takes many versions before an optimized system can be built. When you add in the increase in data, dependencies and complexities of current IP, it only adds to the problem. Examples of complex IP configurations that need iteration include debug & trace, interrupts, interconnect, MMU, memory, I/O etc.
A solution we have been developing at ARM defines an intelligent IP configuration flow to make system integration more scalable and easier to manage. It involves the following:
To enable this concept of intelligent IP configuration, you need tooling to automate the configuration and integration of IP, ensure system viability and reduce the time spent on iterations. ARM® Socrates™ IP Tooling can do this, using what we are calling ‘IP Creators’. ARM IP creators have a unique flow (lifecycle) that includes features such as :
These features accelerates the design cycle (case study shows an 8x reduction), reduces risk and simplifies system design. Let’s take a closer look at how this is done.
First, you need to automatically create the system specification. This is done through harvesting the system data, as well as identifying the interfaces on the particular IP, for example an interconnect. Our current flow will read IP-XACT metadata from a system and be able to infer certain interface configuration for IP e.g. for an interconnect we can extract interface requirements e.g. AMBA® protocol type, data size, address size etc. For debug and trace, we can infer information like the number of ATB interfaces, size etc. This process accelerates the specification of the IP interfaces and will use this information to drive the final IP configuration.
The next step is to define and create the System IP µarchitecture. The system architect can input high level information e.g. data paths, memory maps, and other data that that are processed by algorithms to configure the IP. The µArchitecture synthesis automatically creates the IP in a way that is correct-by-construction, through design rule checks (DRCs) that validate the configuration. You can see in the image below the master/slave connections that are generated by the algorithms.
The major effect of the µArchitecture synthesis is that configuration iterations are greatly reduced. It results in a system assembly process that is faster and easier. Interfaces are automatically AMBA-compliant through the IP-XACT-driven approach to integration. The image below shows a fully connected system resulting from the µArchitecture synthesis.
Once system integration is complete, a number of deliverables are generated that can be easily used by different stakeholders within the design team. The RTL of the integrated system design, testbench, test cases, design spec and reports are all automatically published and ready for the next step of SoC design.
Putting this methodology of intelligent IP configuration and automated IP integration to the test, we conducted some internal studies. Typically the creation of a debug and trace subsystem is a time-consuming and iterative process. When using this new approach, the time spent was dramatically reduced from three months to just one week. Even more impressive was the elimination of 90 bugs when comparing the two approaches, as the intelligent methodology did not return a single bug during the design cycle.
The SoCs that are being designed today have increased dramatically in complexity over the last number of years, and will continue to do so. A combination of smaller process nodes, more complex IP and designs targeting highly specific performance points means that system integration plays an important role in the creation of an SoC. Using an automated tooling methodology based on designer input rules can make system assembly easier and faster. Looking to the future, there is potential for innovation around adding physical awareness as new metadata to enable better PPA analysis and trade-off.