Hi all, I can finally share with you some of the interesting work we have been doing around Cortex-M0 Design Start and FPGA. ARM has re-launched the Cortex-M Design Start program making it more easily accessible and even more affordable. We have worked with our colleagues in the CPU design team to improve our FPGA support for Cortex-M0 substantially. Using our existing Cortex-M Prototyping System (MPS2) and a interesting feature from Altera called partial reconfiguration (PR), we can provide the user with a fully debuggable Cortex-M0 CPU with a user area which you and edit and modify with your IP without a CPU licence. Using the PR feature we have created an 'CPU partition' with full debug feature, to which you can connect your own IP in a 'user partition'. We have provided CMSDK peripherals and an example design in the user area from which you can start from. The 'CPU partition' includes debug but is fixed and encrypted.
You can use the Altera Quartus tool chain to resynthsize your design and provide your own customisable target. The platform comes with mbed drivers for all the peripherals such as SPI, GPIO, UART etc. We have created an application note how this all works. We have also created a FPGA test bench, so you can simulate your design at the target level (e.g FPGA). The simulation test bench requires you to download the obfuscated Cortex-M0 code from the DesignStart page above, but it would be quite useful to debug any of your IP issues ahead of running software at speed.
In addition to this, we have also launched a new version of MPS2 called MSP2+ which is has double the FPGA capacity of the MPS2 board, other that the increase in the FPGA capacity the products are the same, So designs targeted at MPS2, not also have MPS2+ support. Best of all the price remains the same, double the FPGA capacity and no extra cost. Check out the MPS2 page for further information on the platform