Back in April, I wrote about how Atrenta - an ARM Connected Community Partner - was helping to tame the SoC design problem with early power, performance and area or ePPA technology. ePPA holds great promise to help SoC designers hone in on the optimal architecture vey early in the design process - well before detailed implementation begins.
Juggling power, performance and area requirements for an advanced SoC is a daunting task. A critical component in the design equation is the on-chip interconnect. With that in mind, we went to the Design Automation Conference in San Francisco this past June to explain our ePPA strategy to attendees.
We participated in the ARM Connected Community Pavilion at the show, and demonstrated how to take various configurations of ARM's NIC-301 AMBA® on-chip interconnect through the paces of ePPA - resulting in the identification of the optimal on-chip interconnect configuration in a very short time period.
Our demo was very well received and we thank ARM for the opportunity to showcase this work in their pavilion at DAC. You can see a short summary of demonstration below, and view our complete slide presentation. .
We were quite happy with the interest that attendees showed in our ePPA solution. In the months ahead, Atrenta will be working with early adopter customers to help them find the best AMBA configuration for their SoCs.
Guest Blogger:Satish Soman, Chief Solutions Architect at Atrenta Inc. Satish has extensive experience delivering complex SoC designs at start-ups, medium size and large organizations. His expertise spans architecture, design, verification, silicon bring-up and field support. He has held senior management positions at LSI Logic, Digital Equipment Corporation and Nexabit (sold to Lucent for $1B). Satish was the VP of Chip Development for Lucent. He holds 16 patents and received his MS in Computer Engineering from Syracuse University and BS in Electrical Engineering from IIT Bombay.