Cache Coherency and Verification Seminar at DACNow Online!

If you missed DAC, then you missed the seminar on cache coherency and verification of cache coherency given by ARM and Jasper.  Learn how to overcome the typical challenges of capturing the intent, reviewing possible scenarios and how to correct errors in functional terms as they relate to the specification. 

The seminar (on-line recording) kicked off with a discussion on how the implementation of hardware-based coherency in high-performance parallel compute environments is not new.  The seminar quickly revealed that architects and designers of high-performance, heterogeneous, embedded multi-processing SoC's, particularly those with one or more caches and when many masters share a single area of memory, now require robust specifications, design & verification tools and systems IP, to ensure their devices minimize off-chip memory transactions, while maximizing performance and power efficiency.  The seminar then went on to explain why ARM has chosen to include Coherency Extensions within the AMBA 4 ACE specification and the audience was shown an example cache coherent compute sub-system.

  The discussion mentioned above led to some open questions regarding cache coherency verification that were explored in detail. 

• What are the challenges in the verification of coherency specifications?
• What strategies can be used to develop the methodology and VIP required for verification?
• Are the benefits of this verification methodology limited to ARM? How can users take advantage of this methodology?

The answers to these questions describe a novel method for modeling and verifying cache-coherent protocols using Jasper Design Automation technology.  The collaboration between ARM and Jasper also resulted in the development of the interface-level VIP needed to verify RTL designs supporting the ACE protocol.

For more information on cache coherency and verification, please review:

• Webinar of the live seminar
• My earlier blog: Upgrading your Verification for Cache Coherency with Jasper!
• ARM technical blog: The two parts of coherency - data sharing and data movement
• ARM blog: Coherency: the key to boosting future tablets, smartphones and digital TVs
• Jasper whitepaper on cache coherency verification
• ARM whitepaper on cache coherency

Guest Partner Blogger:
Lawrence Loh, Vice President of Worldwide Applications Engineering at Jasper Design Automation,  holds overall management responsibility for the company's applications  engineering and methodology development. Loh has been with the company  since 2002, and was formerly Jasper's Director of Application  Engineering. He holds four U.S. patents on formal technologies. His  prior experience includes verification and emulation engineering for  MIPS, and verification manager for Infineon's successful LAN Business  Unit. Loh holds a BSEE from California Polytechnic State University and  an MSEE from San Diego State.