Beyond traditional ATPG: A test methodology targeting in-cell defects

The goal of silicon testing is to find defective parts before they are shipped to the end user. Key to that testing is to ensure an efficient way to get the best coverage and get quickly to closure. Success is measured in defective-parts-per-million (DPPM), and the lower the number, the better the reliability.

Traditional methods involve adding scan-test structures to a design, then applying fault models to pattern-generation tools that represent issues such as stuck-at faults and transition defects. This provides high defect detection, but mostly for faults at the gate (or cell) boundary are analyzed. An increasing challenge for test teams is that a growing number of defects occur within the cells. These are not explicitly targeted by traditional Automatic Test Pattern Generation (ATPG). N-detect algorithms can potentially test such defects by generating multiple patterns which detect cell-internal defects randomly. However, N-detect algorithms are not efficient with pattern count. Also, Cell-Aware Test (CAT) tries to solve this problem by deterministically targeting every possible internal defect. This results in compact pattern set generation for targeted faults.

This paper shows a comparison of the static and transition patterns that are generated by the CAT methodology. Also, the traditional ATPG for different libraries and cell parameters. The increase in performance, pattern count, and test coverage regarding two Arm designs is also presented, which reflects the actual cost and gains of the CAT model over traditional ATPG.

CAT (Cell-Aware Test) Library Generation

The CAT library generation methodology requires several front-end and back-end views: Cell-wise GDSII, extracted detailed standard parasitic format (DSPF) netlists, gate-level Verilog, and traditional ATPG models. The methodology for layout aware user-defined fault model (UDFM) generation is divided into three steps, which are briefly explained:

Analyze: Assigns fault locations inside the library cell. This is based on the presence of nets and the distance between nets as show in Figure 1.

This step involves analyzing the DSPF netlist extracted with parasitic and location information.

Figure 1: Classification of Cell-internal defects

Simulate - Performs the exhaustive analog simulations to assess how each of the analyzed defects can be detected. The second step in flow involves detailed simulation to evaluate the expected value for every input combination and cross-verification of the Verilog and DSPF. Synthesis aggregates the data that is created in the previous step to generate a UDFM, also shown in Figure 2w, W which can be understood by the ATPG engine or the diagnosis tool. The final step is synthesis which compiles the data from the previous step to group the detectable fault and separate collapsed and non-collapsed faults.

After all the individual cell UDFMs are generated, as shown in Figure 2:  below, they are merged to create a library level view.

 Figure 2: Generation Flow                                             

Advantage of CAT (Cell-Aware Test)

Traditional ATPG models have been in the form of front-end models. These models have been used for all libraries regardless of library features such as channel length, cell height, threshold voltage, drive strength, or extraction temperature. This causes the same patterns to be generated independent of the library or cell variant used. An analysis of the library cell level patterns that are generated while varying the library and cell parameters suggests that the pattern count is greater for CA (Cell-Aware) with respect to traditional SA (Stuck At) and TR (Transition) patterns. The Figure 3, shows variation in pattern generated for different standard cells.

It also covers the variation in patterns regarding the channel length (CL), CL1 and CL2 for extracted cells. Here, 1tf means one-time frame and 2tf means two-time frame. The number present inside the parentheses indicates the number of unique patterns that are generated for the cell. For example, AOI2222 X1 indicates total nine and ten patterns for the CL1 and CL2 variants, out of which five and six are specially created using Cell-Aware.  This shows significant pattern increase using Cell-Aware ATPG.

UDFM helps to uniquely create vectors for a given library and cell configuration, which is missing in the traditional ATPG models. For simpler cells, the variation in the patterns does not affect much. As the complexity increases, unique defects can be created internal to the library cell as shown in Figure 3. This can reduce the DPPM significantly by accurately performing ATPG for more effective patterns.

Library-level statistics

Here, we will compare test coverage with the traditional approach versus CA ATPG at the standard cell library level. Library-level generation of UDFM was done for a 14nm FinFET project. The library is consisting of simple gates, AOI cells, adders, latches, and scan flops. The data that is represented in Figure 4 was derived by loading the traditional ATPG patterns and doing a fault simulation with the UDFM. This data is a ratio of the cell-internal faults that are detected by traditional ATPG and all detectable faults by the UDFM.

Figure 4 CA Transition Fault Coverage with Traditional ATPG

Analysis of 1tf (one-time frame) pattern shows that for simple combinational cells there is no coverage gain with CA pattern as all the cell internal faults are targeted with port patterns. But as cell complexity increase with flops, XOR and XNOR and adder cells, test coverage improves (up to 30%) with CA patterns. For 2tf (two-time frame) patterns, except simple gates like buffers and inverters, we see linear increase in test coverage with increased cell complexity. And the improvement is significant (up to 95%) for 2tf patterns.

CAT on Arm designs

To evaluate the effectiveness and test quality of the CA patterns, the CA ATPG flow was performed on two Arm designs. Design A is an Arm CPU cluster with 260K scan flops. Four CPU cores are stamped in the cluster and test compression logic is inserted. Design B is a configurable coherent interconnect microarchitecture with 509K scan flops. For experimental purposes, no test compression logic is inserted for design B, and only simple scan chains are stitched. The traditional SA TR ATPG and CA ATPG are performed with the Tessent tool from Mentor, a Siemens BusinessGraphics.

Figure 5: Test efficiency with Design A

The left figure in Figure 5 shows that CA patterns can achieve same test coverage with fewer patterns. This is compared to 1-detect or 5-detect approach effectively reducing test cost. The right figure in Figure 5 shows that CA patterns can achieve higher test coverage because some faults that are targeted by CA patterns are never targeted with 1-detect or 5-detect approach.

Cell-aware ATPG targets specifics shorts and opens internal to each library cell, and results show improvement in defect detection. Cell-Aware ATPG has shown gains in test coverage on individual standard cell as well as on Arm designs.  The Cell-aware library can be used for cell-internal diagnosis for any type of patterns, even if there are not any Cell-aware patterns. The Cell-Aware approach helps to increase the test coverage, and therefore it comes with more computational cost; for example, UDFMs need to be generated for Vt/CL variation for accurate diagnosis. Such an effort might be necessary for industry segments targeting high test coverage. Along with improved test coverage, CA ATPG also offers improved diagnosis capabilities.

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