For more than a decade, Arm technology has been designed into critical vehicle safety functions, including anti-lock braking systems, electronic stability programs, and airbags to name a few. And as we move into an era where driving decisions made by artificial intelligence become more commonplace, the relationship technology plays in vehicle safety has never been more crucial.
Functional safety is a foundational pillar for Arm in designing our purpose-built IP for automotive, which requires us to take an end-to-end approach and design with the entire vehicle in mind. Of course, if you are going to design IP for automotive, it’s important to ensure the IP used to optimize it is based on the same principles. A great example of this is our Artisan Physical IP dedicated automotive platform we announced last year, which has been optimized for the implementation of Arm Cortex cores offering the latest industry standards for safety-critical tasks.
Since then, NXP announced the S32 Automotive Processing Platform, powered by Arm Cortex-A, Cortex-R and Cortex-M cores, and has expanded the platform to include the Artisan Physical IP for 16FFC. Vehicle safety remains foundational to an industry that is moving toward automated driving systems and the 16FFC Physical IP platform is designed to help industry leaders like NXP address user-demand for automotive applications like ADAS, infotainment and automated driving, all of which are driving the future of the automotive industry.
Safety is fundamental for advanced automotive applications and any IP considered for NXP’s S32 Platform must not only take the future of automotive into consideration, but do so by meeting stringent automotive requirements to ensure we keep drivers, passengers and pedestrians safe,
Matt Johnson, senior vice president and general manager - Product Lines and Software, Auto MCU and Processors at NXP Semiconductors.
More than enhancing your vehicle’s infotainment system, the Artisan Physical IP for 16FFC includes dedicated memories for automotive applications, and avoids compromises in power, performance and area (PPA), functionality and electrical parameters. Autonomous driving requires that CPUs perform more functions, making high performance a key requirement for OEMs. Arm physical IP is developed to achieve the best PPA for stringent mission profiles, and using FinFETs as the underlying technology is significant because FinFETs can meet high speed requirements while limiting the power and energy consumption of the resulting designs.
As the amount of memory grows on SoCs, special features, such as full scan and optimized timing, improve testability and reliability that are crucial for safety-critical designs like advanced ADAS designs. For OEMs, the faster processors and memories create more opportunity to further “electrify” future vehicles. For drivers and passengers, increasing autonomy without compromising safety and reliability delivers peace-of-mind and a more seamless and complete user experience.
Most importantly, the Artisan Physical IP for 16FFC meets stringent automotive requirements, including the support of the ISO 26262 international standard with optimized features for system ASIL-D functional safety, and the Automotive Electronics Council AEC-Q100 Grade 1 requirements with IP characterized and tested at 150˚C junction temperature. This benefits OEMs by reducing the risk in their solutions; reliability is built into the Artisan physical IP, delivery includes the necessary components to validate at high temperatures, and OEM can focus on the system-level without concern for the underlying IP – this means time and cost savings for bringing designs to market.
The demand for enhanced automotive technology means we should expect compute performance in vehicles to increase by 100x over the next decade – but that can only happen if we continue to acknowledge and ensure that functionality and safety are foundational. The Artisan Physical IP for 16FFC is an example of how we’re building with a solution mindset, and is something we’ve developed for more than 4 years for multiple 55nm and 40nm processes at different foundries; we are in an excellent position to bring what we’ve learned from the industry to help refine the IP and methodology for future developments.
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