Smartphones are now one of the most important consumer electronics devices globally. Smartphone volume shipments are growing at a very healthy rate and are expected to exceed a billion units per annum during 2013. These devices are now often used as a primary and multifaceted compute platform, providing access to the internet, rich multimedia and gaming experiences, content creation, serving as readers for eBooks and magazines, satellite navigation, and of course still continue to be used for their original purpose of communicating, which has expanded from the traditional one-to-one communication into social networking. As computing requirements for mobile devices grow rapidly with each generation, we've seen the recent introduction of ARM® CortexTM-A15 processor-based designs in higher-end mobile products, such as Samsung Galaxy S4, Google Chromebook and Google Nexus 10. This trend will continue as SoC designers compete to create compelling platforms providing ever increasing performance.However, SoC designers have to cope with significant design constraints of mobile systems, requiring careful budgeting of battery capacity, heat dissipation and cost, all while boosting performance and functionality. Naturally, energy efficiency is a very pertinent theme for processors deployed in mobile devices. This week, ARM announced the arrival of the latest member of the ARM Cortex-A Hard Macro family, a power optimized ARM Cortex-A15 dual-core implementation on TSMC 28HPM process. The macro is ideally suited for a wide range of power-sensitive handheld devices such as smartphones and tablets.With the Cortex-A15 MP2 hard macro implementation delivering 10,000 DMIPS and up to twice the performance of smartphones based on the Cortex-A9 processor, the hard macro is a very appealing option for SoC designers aiming to develop an energy efficient Cortex-A15 device that outperforms today's mobile devices. The macro uses several low power features such as DVFS (dynamic voltage and frequency scaling), power gating individual cores when not in use, multiple power domains within the cores, and architectural clock gating.It is equally suitable for a dual-core Cortex-A15 design on its own, or in a big.LITTLE™ processing system accompanied by two or four Cortex-A7 cores. The macro is developed on TSMC 28HPM, which is the process of choice for the mobile market, and is expected to remain so for the next couple of years.Of course, while the technical capabilities of this specific Cortex-A15 hard macro make it attractive to the mobile market, one mustn't forget two of the most important benefits which every ARM hard macro brings to the SoC designer, namely:
As mobile devices become smarter with every generation, designers have to manage the growing complexity under the hood. ARM Hard Macros provide SoC designers ready-to-use IP, which has been fine-tuned to deliver the best possible combination of performance and power for a chosen market and physical process. A lot of expertise and knowledge goes into fine tuning the implementation to derive the best possible results. As most designers understand, achieving the last 20% of the target often takes up 80% of the time. In a highly competitive landscape, the commercial advantages of being early to market cannot be overstated. ARM Hard Macros enable designers to develop their SoC faster, freeing up time to focus on other system components, adding their USP and establishing market leadership through innovative designs and early market penetration. Last year at the launch of the Cortex-A15 MP4 (Quad core) hard macro, my colleague haydnpovey wrote a blog which elaborated further on these benefits. It is no surprise that the MP4 hard macro has now been successfully incorporated in to devices for the enterprise and infrastructure market, and I have no doubt that today's addition to the hard macro family, the Cortex-A15 MP2 will also enjoy similar success in the mobile market.In terms of configuration, the Cortex-A15 MP2 Hard Macro includes:
The hard macro has been developed with the ARM Artisan® 9-track libraries and ARM POP IP™ technology.