Hi ARM Community,
I am currently working on an AHB master driver and have encountered a scenario that I need some clarification on.
In my system, the master driver is configured to set HTRANS = IDLE after completing a burst operation. However, we are facing a situation where the slave driver responds with an error during the last transfer of the burst. Since the master driver transitions to IDLE (HTRANS = IDLE) after the final transfer, my question is:
HTRANS = IDLE
HRESP = ERROR
Additionally, I need clarification on when the master driver should enter the IDLE state after detecting an error. Specifically, when should this happen in the following two cases:
HREADY = 0
IHI0033a/IHI0033C
HREADY = 1
IHI0011A
Could anyone please shed some light on the expected behavior in these cases, and how to handle error responses properly when transitioning to IDLE?
Above Waveforms if Slave Drives HREADY LOW during last transfer then master's Data Phase is able to handle.
Above waveforms if slave driver HREADY LOW and HRESP HIGH, Then Master Cancels next read transfer and starts new write transfer.