• State Accepted Answer
  • +1 person also asked this people also asked this
  • Replies 2 replies
  • Subscribers 26 subscribers
  • Views 1555 views
  • Users 0 members are here
Options
Related
How was your experience today?

Morello: is there an extra timer on the board?

Hesham Almatary

Hello,

Other than the Arm's generic timer, I am wondering if there's an extra timer on the board that could be used (e.g., sp804)? The TRM and DTS (from Linux and TF-A) don't seem to have any. The TRM does mention the SP810_CTRL register used to select the source clock for the SP804 timers in the IOFPGA, but I couldn't find the memory mappings of these timers in the TRM or the DTS.

Regards,
Hesham

Parents
  • +1

    Hi, Hesham.

    There are 2 instantiations of SP804 dual timers in the Morello IOFPGA, so a total of 4 timers - Dual Timer 0 (Timers 0/1) and Dual Timer 1 (Timers 2/3).

    Please refer to the section - 5.2.8 IOFPGA memory map - within the TRM for the memory mapping of the timers. As you've already established, the timer enable control is through SP810 system controller via SP810_CTRL register, the bit encodings for which are described in section - 5.6.13 SP810_CTRL Register - in the TRM.

    It's worth mentioning that the timer interrupts, however, are not routed to the SoC by default. This would require changes in the IOFPGA's configuration file to repurpose a given INT MUX (interrupt mux) to relay the timer interrupt(s) to the SoC (AP).

    Kind regards,
    Anurag

Reply
  • +1

    Hi, Hesham.

    There are 2 instantiations of SP804 dual timers in the Morello IOFPGA, so a total of 4 timers - Dual Timer 0 (Timers 0/1) and Dual Timer 1 (Timers 2/3).

    Please refer to the section - 5.2.8 IOFPGA memory map - within the TRM for the memory mapping of the timers. As you've already established, the timer enable control is through SP810 system controller via SP810_CTRL register, the bit encodings for which are described in section - 5.6.13 SP810_CTRL Register - in the TRM.

    It's worth mentioning that the timer interrupts, however, are not routed to the SoC by default. This would require changes in the IOFPGA's configuration file to repurpose a given INT MUX (interrupt mux) to relay the timer interrupt(s) to the SoC (AP).

    Kind regards,
    Anurag

Children