What is in the October 2021 Maintenance Release of Morello Platform (FVP) model?

Arm made a maintenance release of the Morello Platform Model (FVP) on 21 October 2021. What is in this release?

Parents
  • The Morello FVP 2.0 release includes an enhanced Rainier CPU model with a 2x performance improvement that has been observed while booting Android in comparison to the previously released FVPs. Additionally, the FVP's system architecture has been further aligned with Morello SoC for supporting different types of applications that developers may want to use.

    Here are details of the updates and changes;

    1 - Rainier CPU model changes and improvements:

    • Added DMI support to improve FVP performance up to 2x.
    • Added PMU support.
    • Removed checks for new in bounds to improve performance.
    • Fixed TLB entry to update the SC bit.

    2 - FVP SoC and board alignments:

    • Added a Flash to model AP QSPI.
    • Added a Flash to model MCP QSPI APB.
    • Added a Flash to model SCP QSPI APB.
    • Added the debug sync controller.
    • Increased NS and S ROM address spaces to 512KB.
    • Updated the debug PIK.
    • Added the system counter sync controller.
    • Fixed MMU EMA CTRL default init value.
    • Fixed DPU EMA default init value.
    • Fixed TARGET ID registers.

Reply
  • The Morello FVP 2.0 release includes an enhanced Rainier CPU model with a 2x performance improvement that has been observed while booting Android in comparison to the previously released FVPs. Additionally, the FVP's system architecture has been further aligned with Morello SoC for supporting different types of applications that developers may want to use.

    Here are details of the updates and changes;

    1 - Rainier CPU model changes and improvements:

    • Added DMI support to improve FVP performance up to 2x.
    • Added PMU support.
    • Removed checks for new in bounds to improve performance.
    • Fixed TLB entry to update the SC bit.

    2 - FVP SoC and board alignments:

    • Added a Flash to model AP QSPI.
    • Added a Flash to model MCP QSPI APB.
    • Added a Flash to model SCP QSPI APB.
    • Added the debug sync controller.
    • Increased NS and S ROM address spaces to 512KB.
    • Updated the debug PIK.
    • Added the system counter sync controller.
    • Fixed MMU EMA CTRL default init value.
    • Fixed DPU EMA default init value.
    • Fixed TARGET ID registers.

Children
No data