What is in the June 2021 Maintenance Release of the Morello Architecture Specification?

Arm made a maintenance release of the Morello Architecture Specification on 23 June 2021.

The Morello Architecture Specification release includes documentation and xmls, hence provides fixes to reported bugs and defects.

Updated documentation and xmls are available here: https://developer.arm.com/documentation/ddi0606/aj/?lang=en 

Details of the updates and changes:

• The LDPBR and LDPBLR instruction textual description is corrected to match the ASL to describe the first loaded capability is placed in the destination Capability register, and the second loaded capability is the branch target.
• The ASL for LDR (literal) has been simplified to improve its readability
• R CPRKD has been corrected to reference CCTLR_ELx.TGENy.
• The instruction titles CVT* (non-flag setting) and CVT* (flag setting), are changed to CVT* (to capability) and CVT* (to pointer) respectively. This is to help call out the key differences between these two sets of instructions. I PJKGP and R ZZSZP are added to help differentiate the CVT (to pointer) instruction and and differentiate the behavior with respect to the DDC from R WLPTB.
• R MHJSD, defining the general property that capabilities give no more permission than the base architecture, does not add anything to the specification and so has been removed. A more general statement has been added to the introduction chapter.
• R LBFNG is amended and R BFVBR added to the chapter "The Virtual Memory System Architecture", so that the value of x and y in "TTBRy_ELx" is better contextualized.
• R GCQCJ is corrected, and R JBPWS is added, so that the rules are consistent with the behavior of SEAL (immediate) as described in the pseudocode.
• Feedback has shown that pseudocode with multiple numbered operands, like operand1, operand2, was difficult to understand. This has been improved by changing the names of the pseudocode variables to be descriptive.