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Why does the CMSIS no longer has bitfield for peripheral headers?

Trampas

I started a new project recently and went to get the latest CMSIS packs.  I noticed the peripheral include files no longer include bitfields. I noticed several more changes in the header files and felt like it was a step backwards. I found this change happened when going from CMSIS 2.x to CMSIS 3.x.  I looked around and googled and found no mention as to the change and wondering why it happened? 

Note I assume the change happened because bitfields are messed up in the C language.  That is when you do a bit field write, you are really doing a read, modify, write for the whole register which can create some strange behaviors if you do not understand this.  However I wanted to understand more as to why the change. 

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  • 0 in reply to Broeker

    Thanks I realize this, maybe formed the words incorrectly in my post.  However my question what why the change in the CMSIS?  I personally had to go back to CMSIS 2.x.  The bit field change I understand but many other features and #defines were remove in CMSIS 3.x.   

    For example the CMSIS 2.x had things for my processor like the following which appeared to be removed in 3.x

    /* ========== Instance parameters for SERCOM0 peripheral ========== */
    #define SERCOM0_DMAC_ID_RX          1        // Index of DMA RX trigger
    #define SERCOM0_DMAC_ID_TX          2        // Index of DMA TX trigger
    #define SERCOM0_GCLK_ID_CORE        18      
    #define SERCOM0_GCLK_ID_SLOW        17      
    #define SERCOM0_INT_MSB             6      
    #define SERCOM0_PMSB                3    

    Again I am not looking to fix the problem but rather understand the reason for the change. 

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  • 0 in reply to Broeker

    Thanks I realize this, maybe formed the words incorrectly in my post.  However my question what why the change in the CMSIS?  I personally had to go back to CMSIS 2.x.  The bit field change I understand but many other features and #defines were remove in CMSIS 3.x.   

    For example the CMSIS 2.x had things for my processor like the following which appeared to be removed in 3.x

    /* ========== Instance parameters for SERCOM0 peripheral ========== */
    #define SERCOM0_DMAC_ID_RX          1        // Index of DMA RX trigger
    #define SERCOM0_DMAC_ID_TX          2        // Index of DMA TX trigger
    #define SERCOM0_GCLK_ID_CORE        18      
    #define SERCOM0_GCLK_ID_SLOW        17      
    #define SERCOM0_INT_MSB             6      
    #define SERCOM0_PMSB                3    

    Again I am not looking to fix the problem but rather understand the reason for the change. 

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