I'm looking some code that configures a UART for 115200 baud and assumes that the PCLK to for the UART is 12MHz. Which works fine if my CCLK is 48MHz and the peripheral clock divider is 4.
U1LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit*/
U1DLL = 3; /* for 12MHz PCLK Clock */
U1FDR = 0x67; /* Fractional Divider */
U1LCR = 0x03; /* DLAB = 0 */
That really doesn't work if CCLK is e.g. 72MHz, and this code doesn't work too well either:
Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
U1DLM = Fdiv / 256;
U1DLL = Fdiv % 256;
Has anyone got some code that correctly configures the DLL, DLM and FDR values given a desired baud rate?
The LPC23xx user manual has a flowchart and a lookup table which is pretty scary - I'm hoping someone has done the hard work already
Thanks for coming back to share the solution you found with the community.