code crashes when I include I2C1_IRQ_handler

void I2C1_IRQHandler(void)
{
		I2C1->CR1 &= ~(I2C_CR1_RXIE |I2C_CR1_ADDRIE | I2C_CR1_STOPIE | I2C_CR1_TXIE);
		switch((I2C1->ISR &(I2C_ISR_STOPF | I2C_ISR_ADDR |I2C_ISR_RXNE | I2C_ISR_TXIS)))
		{
			case 0x08: //address match
				dev_addr = ((I2C1->ISR >> 16 ) & 0xFE); // assigning Recieved slave address
				if(I2C1->ISR & I2C_ISR_DIR)
					{
						// Slave address with Read bit
						if(i2c_state == I2C_GOT_CONTROL_WORD_ADDR)
						{
							i2c_state = I2C_REPEATED_START;
						}
						else 
						{
							i2c_state = I2C_RD_STARTED;
						}
						__HAL_I2C_CLEAR_FLAG(&hi2c1,(I2C_FLAG_ADDR ));
						I2C1->CR1 |= (I2C_CR1_TXIE); // enabling Transmitter Interrupt
						//slave Tx
					}
				else
					{
						// Slave address with write bit
						i2c_pkt_length = 0;
						
						i2c_state = I2C_WR_STARTED;
						__HAL_I2C_CLEAR_FLAG(&hi2c1,I2C_FLAG_ADDR);
						I2C1->CR1 |= (I2C_CR1_RXIE); // stopIE is not required
						//slave Rx
						} 
			break;
			case 0x04: //rx data for master
				if(i2c_state == I2C_WR_STARTED)
				{
					CW =I2C1->RXDR;
					word_addr = CW;
					i2c_state = I2C_GOT_CONTROL_WORD_ADDR;
				}
				else
				{
					i2cdatarx[i2c_pkt_length++] = I2C1->RXDR;
					i2c_state = I2C_DATA_STARTED;
				}
				__HAL_I2C_CLEAR_FLAG(&hi2c1,I2C_FLAG_RXNE);
			I2C1->CR1 |= (I2C_CR1_RXIE | I2C_CR1_ADDRIE | I2C_CR1_STOPIE); // enabling Rx address match and Stop interrupt
			break;
			
			case 0x20: // detected a stop
				if (dev_addr == 0xB0 )
				{
					if (i2c_state == I2C_DATA_STARTED || i2c_state == I2C_GOT_CONTROL_WORD_ADDR)
					{
						F0_write(word_addr);
					}
					else 
					{
					I2C1->ISR |= I2C_ISR_TXE;//Setting  flushing the TX buffer for new data transfer
					}
				}
				else
				{
					if (i2c_state == I2C_DATA_STARTED || i2c_state == I2C_WR_STARTED)
					{
						if (mode == mFACTORY)
						{
							A0_write_FM(word_addr); // writting to sram and Eeprom
						}
						else
						{
							A0_write(word_addr);
						}
					}
					else 
					{
					I2C1->ISR |= I2C_ISR_TXE;//Setting  flushing the TX buffer for new data transfer
					}
				}
				i2c_state = I2C_IDLE;
				__HAL_I2C_CLEAR_FLAG(&hi2c1,I2C_FLAG_STOPF);
				I2C1->CR1 |= (I2C_CR1_ADDRIE); // enabling address match 
			break;
			case 0x02: // Transmit has detected
					
					//i2cdatarx = I2C_read_F0(CW);
					if (dev_addr == 0xB0)
					{
						I2C1->TXDR = F0_Read(CW);
					}
					else
					{
						if (mode == 1)
							{
						I2C1->TXDR = A0_read_FM(CW);
							}
						else
							{
							I2C1->TXDR = A0_read(CW);	
							}
					}
				__HAL_I2C_CLEAR_FLAG(&hi2c1,(I2C_FLAG_ADDR));
				I2C1->CR1 |= (I2C_CR1_STOPIE | I2C_CR1_TXIE);
			break;
		}
}