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Cannot Start Program Without Debug

I use a simple delay clock code. But whenever I use this code program won't start without entering debug mode in KEIL. I plug stlink out and reconnect but it wont work if I don't enter the debug mode. Is there any solution to this. If not then what else can I use to have 100 us delay. Thank you for reading

			      uint32_t startTick = DWT->CYCCNT,
             delayTicks = 100 * (SystemCoreClock/1000000);

       while (DWT->CYCCNT - startTick < delayTicks);

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Westonsupermare Pier over 5 years ago +3 verified

You need to enable the functional blocks involved, the debugger does this for itself. CoreDebug->DEMCR |= 0x01000000; // TRCENA DWT->LAR = 0xC5ACCE55; // unlock on CM7 cores DWT->CYCCNT = 0; // reset...

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0 Westonsupermare Pier over 5 years ago in reply to iraquois

Depends on the model of Cortex-M, which you didn't specify. With the CM7 it must be unlocked

From ...\CMSIS\Include\core_cm7.h


data-mode="text">/** Data Watchpoint and Trace (DWT) definitions for the Data Watchpoint and Trace (DWT) type to access the Data Watchpoint and Trace Register (DWT). /*!< Offset: 0x000 (R/W)  Control Register */ /*!< Offset: 0x004 (R/W)  Cycle Count Register */ /*!< Offset: 0x008 (R/W)  CPI Count Register */ /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */ /*!< Offset: 0x010 (R/W)  Sleep Count Register */ /*!< Offset: 0x014 (R/W)  LSU Count Register */ /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */ /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */ /*!< Offset: 0x020 (R/W)  Comparator Register 0 */ /*!< Offset: 0x024 (R/W)  Mask Register 0 */ /*!< Offset: 0x028 (R/W)  Function Register 0 */ /*!< Offset: 0x030 (R/W)  Comparator Register 1 */ /*!< Offset: 0x034 (R/W)  Mask Register 1 */ /*!< Offset: 0x038 (R/W)  Function Register 1 */ /*!< Offset: 0x040 (R/W)  Comparator Register 2 */ /*!< Offset: 0x044 (R/W)  Mask Register 2 */ /*!< Offset: 0x048 (R/W)  Function Register 2 */ /*!< Offset: 0x050 (R/W)  Comparator Register 3 */ /*!< Offset: 0x054 (R/W)  Mask Register 3 */ /*!< Offset: 0x058 (R/W)  Function Register 3 */ /*!< Offset: 0xFB0 (  W)  Lock Access Register */ /*!< Offset: 0xFB4 (R  )  Lock Status Register */

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0 Westonsupermare Pier over 5 years ago in reply to iraquois

Depends on the model of Cortex-M, which you didn't specify. With the CM7 it must be unlocked

From ...\CMSIS\Include\core_cm7.h

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
  @{
 */

/**
  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
 */
typedef struct
{
  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
        uint32_t RESERVED0[1U];
  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
        uint32_t RESERVED1[1U];
  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
        uint32_t RESERVED2[1U];
  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
        uint32_t RESERVED3[981U];
  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
} DWT_Type;

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