Our team has developed a custom SoC with embedded flash blocks and a Cortex M0. Given that the code flash download routine will have to be customized, I am looking for some help and information on how to get started. The SoC as a 2 wire SWD interface built-in.
We are planning to use the Keil IDE and a Jlink debugger hardware. I am relatively new in this and might not be using the right technical terms, so do correct me if some of the questions are ambiguous.
Questions I have are
1. Given that most of the IDEs and Flash Programmers only define routines for known mainstream products; how do I get my compiled code into my custom Soc through the SWD interface?
2. Is there a platform where we can write SWD commands and include it into Keil as part of flash download routine?
3. Will code debugging / breakpoint still work with a custom routine?
4. Otherwise, do I need to run a separate Flash Programmer software ?
Thank you in advance for all inputs.
Hi West,
Thanks for the quick reply. Things are starting to get a little clearer now.
I will have to find out what debug build options were used for our core, thanks for pointing that out.
Also good to know the debugger is code memory agnostic.
I suppose having 8K of internal RAM is sufficient for the flash loader applet?
I have always thought that the flash loader is something done at Keil or the debugger Jlink level and what it does is to generate corresponding SWD operations directly the M0 processor.
Is there some material somewhere that I can refer to have an idea how the flash loader applet (in the target) interacts with commands/inputs coming in from Keil/Jlink through the SWD?
ARM provides SWD protocol information to IP licencees, there are also application notes / docs for debugger writers.
Suffice to say the connection allows registers within the core to be read, written, access to memory/buses, and execution of code. Links to flash loader development docs/info were provided earlier, additional material can be searched from there.
The FLASH implementation is outside the core, what and how it works depends on how it was designed, and is not the responsibility of ARM, Keil or Segger to implement. Usually SoC development teams have staff with responsibilities for various implementation, integration, testing and coding. Keil and TI, for example, might work together on parts that sell millions of units. ACME Random ASIC Co. less so, and likely to incur NRE charges to provide engineering support/services.
Noted. Will explore those links you provided.
Thank you for your help so far.