PWM for FRDM KL25Z board

#include "MKL25Z4.h"                    // Device header

/*
PTB18 -> TM2 CH0
PTB19 -> TM2 CH1
*/

#define PTB18_Pin	18
#define PTB19_Pin	19
#define PTB18_PWM_Ch	0
#define PTB19_PWM_CH  1

#define MASK(x)         (1 << (x))

/* intiPWM() */
void initPWM(void)
{
		//Enable Clock Gating for PORTB
		SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
	
		// Configure Mode 3 for the PWM pin operation
		PORTB->PCR[PTB18_Pin] &= ~PORT_PCR_MUX_MASK;
		PORTB->PCR[PTB18_Pin] |= PORT_PCR_MUX(3);
	
		PORTB->PCR[PTB19_Pin] &= ~PORT_PCR_MUX_MASK;
		PORTB->PCR[PTB19_Pin] |= PORT_PCR_MUX(3);		
	
		// Enable Clock Gating for Timer2
		SIM->SCGC6 |= SIM_SCGC6_TPM2_MASK;
	
		// Select clock for TPM module
		SIM->SOPT2 &= ~SIM_SOPT2_TPMSRC_MASK;
		SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // MCGFLLCLK or MCGPLLCLK/2
		SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK;
		SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL(0); // MCGFLLCLK
	
		// Set Modulo Value 48000000 / 128 = 375000 / 7500 = 50 Hz
		TPM2->MOD = 7500;
		
		// Update SnC register: CPWMS=1, CMOD = 01, PS=111 (128)
		TPM2->SC &= ~((TPM_SC_CPWMS_MASK) | (TPM_SC_CMOD_MASK) | (TPM_SC_PS_MASK));
		TPM2->SC |= (TPM_SC_CPWMS(2) | TPM_SC_CMOD(1) | TPM_SC_PS(128));

		TPM2_C0SC &= ~((TPM_CnSC_ELSB_MASK) | (TPM_CnSC_ELSA_MASK));
		TPM2_C0SC |= (TPM_CnSC_ELSB(1));
}

/* MAIN function */

int main(void)
{
		SystemCoreClockUpdate();
		initPWM();
	
		TPM2_C0V = 0x8000;
	
		while(1)
		{}
}