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Bug in NVIC_GetPriority (Cortex-M0) ?

c xh

Hi,

Here is the return statement in Cortex-M0's function NVIC_GetPriority ----

__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{

  if(IRQn < 0) {
    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
  else {
    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
}

It does not shift off the heading bits of other IRQs.
for example, if IRQn == 26 and NVIC->IP[ _IP_IDX(IRQn)] == 0x40404040,
it return 0x101.
The correct priority value should be 1.

__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{

  if(IRQn < 0) {
    return 0xFF & ((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
  else {
    return 0xFF & ((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
}

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  • 0 in reply to doubt that my ISP Al Bradford

    I don't think it's the correct attitude ..

    Well now. Lets examine the evidence shall we. You have posted what you think is a bug on a forum not guaranteed to be monitored or even looked at occasionally by Keil staff. You then say that the people who have probably looked at what you wrote have got an incorrect attitude.

    From this I can correctly conclude that you are an idiot.

    Stop wasting our time. Goodbye.

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