enable_irq()/disable_irq() in ARMCC V4

http://www.keil.com/support/man/docs/armcc/armcc_Chdgddcj.htm

Restrictions on inline assembly operations

Some low-level features that are available in the ARM assembler armasm, such as branching and writing to PC, are not supported.

Registers such as r0-r3, sp, lr, and the NZCV flags in the CPSR must be used with caution. If you use C or C++ expressions, these might be used as temporary registers and NZCV flags might be corrupted by the compiler when evaluating the expression. See Virtual registers.

The pc, lr, and sp registers cannot be explicitly read or modified using inline assembly code because there is no direct access to any physical registers. However, you can use the following intrinsics described in the Compiler Reference Guide to access these registers:

I did not notice this:
http://www.keil.com/support/man/docs/armcc/armcc_Chdgbbia.htm
There is no virtual Processor Status Register (PSR). Any references to the PSR are always to the physical PSR.

Hope my second try would be better.
infocenter.arm.com/.../index.jsp

Note that CPSR_c is used instead of CPSR in the MSR instruction, to avoid altering the condition code flags.
A better implementation is:

/* NewState=1 will enable IRQ, NewState=0 will disable IRQ */
/* ARM core must be in a privileged mode, e.g. supervisor  */
void ChangeIRQ(unsigned int NewState)
{
    int my_cpsr;

    __asm
    {
    MRS my_cpsr, CPSR                        /* get current program status */
    ORR my_cpsr, my_cpsr, #0x80              /* set IRQ disable bit flag */
    BIC my_cpsr, my_cpsr, NewState, LSL #7   /* reset IRQ bit with new value */
    MSR CPSR_c, my_cpsr                      /* store updated program status */
    }
}

which compiles into:

ChangeIRQ
    MRS r1,CPSR
    ORR r1,r1,#0x80
    BIC r0,r1,r0,LSL #7
    MSR CPSR_c,r0
    MOV pc,lr

A corrected link to the mentioned code:
infocenter.arm.com/.../index.jsp