Ok be nice, this is my first time using a uP. For the XC167 eval board, the (256k x 16bit)SRAM memory is setup like this. The xc167 A18 through A1 goto A17-A0 on the memory, and the 167 A0 goes to L\B\ (lower byte enable) on the memory. Instead of using up 256k addresses isn't it using 512k? 256k for upper bytes, and 256k for lower bytes? why are they doing it this way? Cant you use a separate CS to read/write lowerbytes? the XC167 has high byte write and enable strobe, but nothing for the lower byte. Is it common to do it this way then? Was I wrong when I read 12MB of external memory and assumed that it meant 12M x 16 bit which would really be 24MB. I guess it makes sense now. But If I wanted to could I use a CS to double my memory? not that I'm going to..........
the datasheet XC167CI Data Sheet , V1.1, Jun. 2003 http://www.infineon.com/upload/Document/xc167_ds_v1.1_2003_06.pdf?BV_SessionID=@@@@0398082869.1123882762@@@@&BV_EngineID=ccckaddfglillegcflgcegndfifdfoi.0 states on page 20 All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes1), which are as follows: – 16 … 24-bit Addresses, 16-bit Data, Demultiplexed – 16 … 24-bit Addresses, 16-bit Data, Multiplexed – 16 … 24-bit Addresses, 8-bit Data, Multiplexed – 16 … 24-bit Addresses, 8-bit Data, Demultiplexed In other words the device can be programmed to behave either way The above modes gives you a choice between a "straight forward 16 bit non-multiplexed" access which will reduce the number of I/O pins for other purposes or in the other end of the spectrum "old standard 8 bit multiplexed" which, while making external memory access more involved (slower) free up some pins for I/O. So to answer your question: "that depends" Have a great weekend Erik PS did you ask "the programmer" about RAM and ROM (flash) and you talk abour 256*16 I referred you to 512*16