This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cyclic Redundancy Check

Does anybody has a code of Cyclic Redundancy Check implemented in assembly??

Parents
  • Write a procedure that performs CRC
    computation. The same procedure should be used for
    CRC computation at the transmitter and the receiver. The procedure should perform
    computation on frames with size multiple of 8 bits and a maximum of 127 bytes. You would
    also need a macro to rotate an array of up to 127 bytes by one bit.
    CRC Computation at the source is performed as follows; since a 16 bit standard polynomial
    is used, 16 zeros are appended to the end of the k-bit frame. The (k+16) bits are supplied to
    the CRC circuit as shown in figure 3. After (k+16) shifts the remainder value obtained in the
    shift register is the CRC. This value is simply appended to the k bits of the original message.
    At the destination, the circuit performs the same operation on the received (k+16) bit frame,
    without appending zeros. An error is reported only if the remainder value is different than
    zero.
    A file needs to be divided into blocks of 127 bytes, the last block may have less than 127
    bytes. The error control operation has to be performed on the already encrypted data.
    This phase can be performed without having to link the two computers together. Tests should
    be carried out and results reported.

Reply
  • Write a procedure that performs CRC
    computation. The same procedure should be used for
    CRC computation at the transmitter and the receiver. The procedure should perform
    computation on frames with size multiple of 8 bits and a maximum of 127 bytes. You would
    also need a macro to rotate an array of up to 127 bytes by one bit.
    CRC Computation at the source is performed as follows; since a 16 bit standard polynomial
    is used, 16 zeros are appended to the end of the k-bit frame. The (k+16) bits are supplied to
    the CRC circuit as shown in figure 3. After (k+16) shifts the remainder value obtained in the
    shift register is the CRC. This value is simply appended to the k bits of the original message.
    At the destination, the circuit performs the same operation on the received (k+16) bit frame,
    without appending zeros. An error is reported only if the remainder value is different than
    zero.
    A file needs to be divided into blocks of 127 bytes, the last block may have less than 127
    bytes. The error control operation has to be performed on the already encrypted data.
    This phase can be performed without having to link the two computers together. Tests should
    be carried out and results reported.

Children