In 8051 1 machine cycles = 12 CLK cycles 2 ALE pulse produced in 1 M/Cycle does it means that both opcode fetch and memy read can be performed in 1 m/cycle if needed? T state = subdivision of operation performed in 1 CLK cycle. Please clarify if my ideas are right. Thank you NITIN
hi, is the question not related to Keil, yeah? You should read C51 hardware manual which says you that external data memory read/write cycles take twice more time than program fetch (at "basis" model of C51). By other words, due MOVX to external memory, second fetch is replaced with RD/WR cycle. cu