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Hello everyone,
I am trying to make communication between an STM32F3 microcontroller and a custom board baser on PIC microcontroller using SPI protocol.
The STM32F3 acts as a Slave and the custom board as a Master. The clock is set to 10 MHz. I’m using NSS hardware, and getting EXTI once CS gets low in NSS pin. The CPOL and CPHA are compatible between the two boards. I am using Interrupt base communication in the Slave side. The application consists of: 1) The Master sends a command to the Slave, then a data of 4 bytes : This part works fine 2) The Master sends continuously different commands, The Slave process the command, then sends its proper data (4 bytes) depending on the received command. The Updating frequency sends by the Master is about 20 KHz.
I have a problem with the second case, in fact, when the Master sends a command, let’s say 0x01, the Slave process this address and then sends back a frame let’s say 0x410547AF.
In the MISO line the frame is shifted, c.a.d (0x47, 0xAF, 0x41, 0x05, 0x05) instead of (0xXX, 0x41,0x05, 0x47, 0xAF), because the first byte corresponds to the byte when the address is received. I also used the debug mode to view the SR register and I can see that the FIFO transmission level is always at 2, that explains why the frame is shifted by 2 bytes. But I can’t find a solution to my problem, do you have an idea what would be the problem please? If you want some code sample, I can post it. I hope that my problem is clear. Thanks in advance Best regards
It supports a hardware slave select but the Master(a custom board) toggles the chip select line manually. This is why, i use Trigger_Rising_Falling to detect the Low and High level to synchronize the communication.
That reasoning is seriously flawed. How the master organizes outputting the slave select signal has no relevance whatsoever as to how the slaves handles inputting it.
There's not generally any time to spare on unnecessary interrupt handling when you're implementing a slave device for any serial protocol, and high-bitrate SPI is about the most critical of them all unless you have specialized hardware support for it (DMA and/or a FIFO). And if you do have such support, you still have to configure that exactly right, or it'll make things worse instead of better. At this point it appears you're failing on that latter count.