Can any one help me with calculation of PCLK for UART (baud rate of 9600)
According to datasheet if LPC2148 PLL calculations are as follows: 1.CCLK = M × FOSC 2.FCCO = CCLK × 2 × P
but they have not mentioned how to calculate PCLK.
Can any one help me with above calculation of PLCK
It depends on the APB Divider Setting.
See the UM10139 LPC214x User manual Chapter 4: LPC214x System control
4.11 APB divider The APB Divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB Divider serves two purposes. The first is to provides peripherals with desired PCLK via APB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the APB bus may be slowed down to one half or one fourth of the processor clock rate. Because the APB bus must work properly at power up (and its timing cannot be altered if it does not work since the APB divider control registers reside on the APB bus), the default condition at reset is for the APB bus torun at one quarter speed. The second purpose of the APB Divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. The connection of the APB Divider relative to the oscillator and the processor clock is shown in Figure 12. Because the APB Divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.