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DAC without DMA and TIMer

Hi , i'm tryiing to use a simplest sample for DAC in stm32 , so i choose the non-triggerd is the simplest way : Digital to Analog conversion can be non-triggered using DAC_Trigger_None and DAC_OUT1/DAC_OUT2 is available once writing to DHRx :

so seems i missed some thing knowinh that i declared the oclock in an other file :

< /* Includes ------------------------------------------------------------------*/

#include "stm32f2xx.h"

#include "stm32f2xx_gpio.h"
#include "stm32f2xx_dac.h"

/* Private define ------------------------------------------------------------*/
#define DAC_DHR12R2_ADDRESS 0x40007414
#define DAC_DHR8R1_ADDRESS 0x40007410

DAC_InitTypeDef DAC_InitStructure;

void DAC_Config(void)
{ GPIO_InitTypeDef GPIO_InitStruct;

/* GEPIO CONFIGURATION of DAC Pin */

GPIO_InitStruct.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AN;
GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOA, &GPIO_InitStruct);

/* GEPIO CONFIGURATION of input Pin for DHR */

GPIO_InitStruct.GPIO_Pin = GPIO_Pin_1 |GPIO_Pin_0|GPIO_Pin_2|GPIO_Pin_3| GPIO_Pin_4|GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7 ;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOD, &GPIO_InitStruct);

/* DAC channel1 Configuration */ DAC_InitStructure.DAC_Trigger = DAC_Trigger_None; DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None; DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; DAC_Init(DAC_Channel_2, &DAC_InitStructure);

/* Enable DAC Channel2 */ DAC_Cmd(DAC_Channel_2, ENABLE);

}

int main (void) { uint16_t DATA ;

while (1) { DATA = GPIOD ->IDR ; /* Set DAC channel2 DHR12RD register */ DAC_SetChannel2Data(DAC_Align_12b_R, DATA);

}

}

>

Parents
  • my data in the FPGA is a voltage [32 bits] i want to test this voltage but i must read only the high bit [0 12] V(0) V(1) V(2) ....V(11) So my idea is get the V(0) like an input to the stm32 ie V(0)-> GPIOD_Pin_0 and ....

    But think about this very carefully. GPIOD_Pin_0 is expecting the LOWest order bit, you are telling me V(0) is the HIGHest order bit, you understand why I think this is BACKWARD?

    You write 4095 (0x0FFF) to the DAC you expect the output to be approximately VREF (3V?), you change the LOW bit so you get 4094 (0x0FFE) you drop 1/4096th of VREF, so the output will still be practically VREF (3V)

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  • my data in the FPGA is a voltage [32 bits] i want to test this voltage but i must read only the high bit [0 12] V(0) V(1) V(2) ....V(11) So my idea is get the V(0) like an input to the stm32 ie V(0)-> GPIOD_Pin_0 and ....

    But think about this very carefully. GPIOD_Pin_0 is expecting the LOWest order bit, you are telling me V(0) is the HIGHest order bit, you understand why I think this is BACKWARD?

    You write 4095 (0x0FFF) to the DAC you expect the output to be approximately VREF (3V?), you change the LOW bit so you get 4094 (0x0FFE) you drop 1/4096th of VREF, so the output will still be practically VREF (3V)

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