Upon activation of an interrupt, the microcontroller goes through the following steps 1. It finishes the instruction it is executing and saves the address of the next instruction (PC) on the stack 2. It also saves the current status of all the interrupts internally (i.e: not on the stack) 3. It jumps to a fixed location in memory, called the interrupt vector table, that holds the address of the ISR this is available in mazithi's book's,look at the highlighted case,if not in the stack where it ll be saved
It simply means that the related Flags in the SFRs are set. TF0 flag for Timer0, TF1 flag for Timer1 and so on....
For the 8051, the so-called "vector" table holds code to be executed - not the address of the ISR (as for many other architectures).
To make a jump from the so-called "vector" location, you have to code a Jump instruction...
It also saves the current status of all the interrupts internally (i.e: not on the stack)
A miserable attempt to make something understandable by stating an outright lie.
No interrupt requests are "lost at interrupt"
what many misunderstand is that e.g. a timer can directly cause an interrupt.
the way all interrupts in the '51 architecture are handled is as follows () will refer to T0
when a device wants to cause an interrupt it set a flag (TF0) indicating an interrupt request
between every instruction the interrupt peocessor examines all interrupt requests and if one or more exist generates an interrupt for the highest priority one.
regarding your reply,
but when ISR in execting,at the time no interrupt will be accepted know,after completion of the current ISR only the controller will be ready to accept the new interrupt,is n't it?
after completion of the current ISR only the controller will be ready to accept the new interrupt,is n't it? Dont we know any thing about Interrupt Priorities?
Dont we know any thing about Interrupt Priorities?
if you read 'the bible' you do