STM32F103RB problem with TIM2 interrupt on DMA USART

Hi,
I am having problems with STM32F103RB in MCBSTM32 with Keil UVision.
I am trying to use the TIM2 interrupt on DMA USART with tasks. The problem is that the interrupt never happen. Sure that I am missing something.
I put the resume of the code below and all the project and stuff on .rar. I use the file STM32_Init.c
I test the code sending stuff by the serial port and the interrupt didnt occur. When I set the os_event_set I receive stuufs, the code works.

The project:
www.4shared.com/.../TASK_INTERRUPT_MODBUS.html

 *----------------------------------------------------------------------------*/
#include <RTL.h>                      /* RTX kernel functions & defines      */
#include "stm32f10x_lib.h"            /* STM32F10x Library Definitions       */
#include "STM32_Reg.h"                /* STM32 register and bit Definitions  */
#include "STM32_Init.h"               /* STM32 Initialization                */
#include "LCD.h"                      /* LCD functions prototypes            */
#include "stm32f10x_nvic.h"
#include "stm32f10x_it.h"

__task void task_init     (void);
__task void task_rece_USART (void);
__task void task_display (void);
OS_TID tsk3,tsk4;


void NVIC_Configuration(void)
{
  NVIC_InitTypeDef NVIC_InitStructure;

#ifdef  VECT_TAB_RAM
  NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
#else
  NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
#endif

  NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel5_IRQChannel;
  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  NVIC_Init(&NVIC_InitStructure);


  NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel4_IRQChannel;
  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  NVIC_Init(&NVIC_InitStructure);
}

void DMA_UART_Init (void) {

  RCC->AHBENR |= (1<<0);                       /* enable periperal clock for DMA       */
  /* Enable DMA channel5 IRQ Channel */

  DMA1_Channel5->CMAR  = (unsigned long)& Recepcao_Modbus[0] ; /* set chn1 memory address     */
  DMA1_Channel5->CPAR  = (unsigned long)&(USART1->DR);     /* set chn1 peripheral address */
  DMA1_Channel5->CNDTR = 100;                     /* transmit 3 words                     */
  DMA1_Channel5->CCR   = 0x00000082;            /* configure DMA channel 1              */
                                                /* circular mode, memory increment mode */
                                               /* memory & peripheral size 16bit       */
                                               /* channel priotity high                */

  DMA1_Channel4->CMAR  = (unsigned long)& Mensagem_Modbus[0] ; /* set chn1 memory address     */
  DMA1_Channel4->CPAR  = (unsigned long)&(USART1->DR);     /* set chn1 peripheral address */
  DMA1_Channel4->CNDTR = 0;                     /* transmit 3 words                     */
  DMA1_Channel4->CCR   = 0x00000092;            /* configure DMA channel 1              */
                                               /* circular mode, memory increment mode */
                                               /* memory & peripheral size 16bit       */
                                               /* channel priotity high                */


  USART1->CR1 = 0x0000200C;
  USART1->CR2 = 0x00000000;
  USART1->CR3 = 0x00C0;
  USART1->BRR = 0x1D4C;

  DMA1_Channel5->CCR  |= (1 << 0);              /* enable DMA Channe1                   */

}

 __task void task_init (void)  {

  tsk4 = os_tsk_create (task_display, 2);
     tsk3 = os_tsk_create (task_rece_USART, 3);

  os_tsk_delete_self();               /* End      initialization task        */
}



__task void task_display (void)  {
 for (;;) {


      //lcd_clear();
      set_cursor(0,1);
      lcd_print ("         Task2");

    /*
      sprintf(msg_buf, "%d ", tim2_teste);
      set_cursor(0,1);
      lcd_print(msg_buf);

    */
           os_dly_wait (10);
                 /* Wait 100 ms and display again       */
    //   os_evt_set (0x0001, tsk3);

    }
}
__task void task_rece_USART (void){
  unsigned int indice_modbus = 0, max, tamanho_pedido;
  unsigned int CRC2, crc_hi, crc_low, ind, des;
  unsigned char *ptr_char;

 for (;;)  {

        if (os_evt_wait_or (0x0001, 0xFFFF)){              //INTERRUPT NEVER HAPPEN
        os_evt_clr (0x0001, tsk3);
        code.....
}
}

int main (void) {
  //int i;

  OFFSET_aux = (int)(OFFSET *0.02);

  stm32_Init ();                      /* STM32 setup                         */

  TIM2->CR1 = 0x0000;

  NVIC_Configuration();

  DMA_UART_Init();


  os_sys_init (task_init);            /* Initialize OS and start init task   */

  }
///////////////////////////////////////stm32f10x_it.c/////////////////////////////////////////////
void DMA1_Channel4_IRQHandler(void){

    if((DMA1->ISR & 0x00001000) || (DMA1->ISR & 0x00002000)) {
        DMA1->IFCR = 0x00001000;
        DMA1_Channel4->CCR   = 0x00000092;            /* configure DMA channel 4              */
        DMA1_Channel4->CNDTR = 0;
        DMA1_Channel5->CCR   = 0x00000082;            /* configure DMA channel 1              */
        DMA1->IFCR = 0x00010000;
        DMA1_Channel5->CNDTR = 100;                     /* transmit 3 words                     */
        DMA1_Channel5->CCR  |= (1 << 0);              /* enable DMA Channe1                   */

    }
}

void DMA1_Channel5_IRQHandler(void){

    if((DMA1->ISR & 0x00010000) || (DMA1->ISR & 0x00020000)) {
        DMA1_Channel5->CCR   = 0x00000082;            /* configure DMA channel 1              */
        DMA1->IFCR = 0x00010000;
        DMA1_Channel5->CNDTR = 100;                     /* transmit 3 words                     */

    }
}
void TIM2_IRQHandler(void)
{
    if ((TIM2->SR & 0X0041) == 0x0041){
        TIM2->CNT = 0;
        TIM2->CR1 = 0x0001;
        TIM2->SR &= 0xFFBE;
    }else{
        if (TIM2->SR & 0x0001){
            TIM2->CR1 = 0x0000;
            DMA1_Channel5->CCR   = 0x00000082;
            TIM2->SR &= 0XFFFE;
            isr_evt_set (0x0001, tsk3);
        }
    }
///////////////////////////////////////stm32f10x_it.c/////////////////////////////////////////////