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Hi, I'm developing a piece of kit using an STM32F207, and running the RL-RTX. I'm using the IWDG as I develope the F/W further. I perform daily/nightly soak tests on blasting data packets through the device and most of the time everything's tickety-boo. However, occasionally, just occasionally I get a reset caused by an IWDG timeout. I know this because I test for it on a reset, and count them.
Clearly this is unacceptable. So I'd like to capture the stack pointers before the device performs the IWDG reset (so that I have an idea where it's falling over). I was thinking that I might be able to read the MSP/PSP registers at the point where the "Reset_Handler" starts, but I'm not sure this will work as they may be cleared by the silicon at the point of reset. Also I'd have to store the captured values to somewhere safe like the RTC backup registers.
Remember, an IWG performs a reset on timeout. Nothing more.
Has anyone out there also wanted to do this ? Did they have a cunning plan ? ...and an even more cunning solution ?
All pointers, help, comments, are most welcome.
Best, Rich.
...rump ? did I say rump ? I meant dump of course.
Hi Tamir, thanks for the response. It's always nice to known that someone has taken the time to read my stuff/guff.
Anyhoo, to my knowledge the cortex-m series do not implement shadow registers. Instead, for exception handling, they use a fast (H/W implemented) stacking scheme where an 8-word stack frame is created of r0-r3, r12, lr, pc, xPSR.
So, I've tried this :-
a). grab the PSP at the Reset_Handler. i.e the first thing it does is "MRS r0, PSP" b). call a function that i). checks that the IWDG flag caused the reset. ii). grabs the PC from the PSP stack frame. iii). writes the PC to an RTC backup register. c). return and continue with Reset_Handler.
It might work. I've left it soaking over the weekend. Let's see what turns up on Monday morning.
Have a goodun, Rich.
In the register WWDG->CFR you can set the bit WWDG_CFR_EWI (Early wakeup interrupt) - this comes 1 cycle before the WWDG and as far as I understand ref manual 18.3 (in chip STM32F407 - I hope it works also for your chip), the WWDG will reset the device only after end of this interrupt - so you could even easily set a breakpoint in this interrupt (if your debugger is active during your testing).