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LPC1769 USB DMA Mode

Shaunak Shilimkan

Hi,
I am currently using IN EP3 of the LPC1769 to realize Isochronous transactions to the Host. I have configured the this endpoint in the DMA mode

 LPC_USB->EpDMAEn   = 0x80;

I enable the DMA on the EP when I receive the Set Interface command from the Host. However, I see that the EpDMAEn does not change its value to 0x80 as desired (this could probably be because the register is Write Only, but I am not sure).
Please can someone let me know the conditions under which the DMA mode for the EP would get disabled?

In order to get around this problem I write to the above register everytime I create a DMA Descriptor. Is this a good method? Many time we end up loosing bytes of information on the host but I am not sure if it is actually because of this.

Any help in this regard would be much appreciated.

Thanks very much.

Regards,
Shaunak

Parents
  • 0 in reply to Chinzei Tsuneo

    Hi Tsuneo,

    Thanks for your reply. We are actually using Win CE Development board as the Host. We do not have a sniffer to view packets transferred over USB for Win CE.

    However, I had a few more questions.

    I have created a DMA decriptor for the Isochronous endpoint. We intend to transfer 1284 bytes of data over the IN Isochronous Endpoint via 2 burst of 642 each. The descriptor is as follows

    Next_DD = 0x00000000
DMA_mode = 0x00
Next_DD_valid = 0
Isochronous_endpoint = 1
Max_packet_size = 0
DMA_buffer_length = 2
DMA_buffer_start_addr = Start address of Data buffer to be transferred
DD_retired = 0
DD_status = 0
Packet_valid = 0
LS_byte_extracted = 0
MS_byte_extracted = 0
Message_length_position = 0
Present_DMA_count = 0
Isochronous_packetsize_memory_address = pointer to the address containing the following data 0x00000282; There are 2 locations at consecutive word boundaries having the same value;


    Please could you let me know following?
    1. The DMA transfer for a burst of 642 bytes will begin after teh corresponding bit in USBDMARSt is set (FRAME 1ms trigger). Will the second transfer soon follow this transfer or will the second burst trasfer take place only after the bit in the USBDMARSt register is set again (FRAME 1ms trigger)?
    2. If the first DMA transfer to the EP RAM has completed but hasn't been read by the host through an in transaction, will the next DMA transfer over-write the data transferred during the first burst?
    3. If the Host is in the process of reading the data from the IN Isochronous EP, and the 2nd DMA burst is initiated will the data being transfer to the host get corrupted?

    Please see the following post. The message is too long to be completed in a single post.
    Thanks very much

Reply
  • 0 in reply to Chinzei Tsuneo

    Hi Tsuneo,

    Thanks for your reply. We are actually using Win CE Development board as the Host. We do not have a sniffer to view packets transferred over USB for Win CE.

    However, I had a few more questions.

    I have created a DMA decriptor for the Isochronous endpoint. We intend to transfer 1284 bytes of data over the IN Isochronous Endpoint via 2 burst of 642 each. The descriptor is as follows

    Next_DD = 0x00000000
DMA_mode = 0x00
Next_DD_valid = 0
Isochronous_endpoint = 1
Max_packet_size = 0
DMA_buffer_length = 2
DMA_buffer_start_addr = Start address of Data buffer to be transferred
DD_retired = 0
DD_status = 0
Packet_valid = 0
LS_byte_extracted = 0
MS_byte_extracted = 0
Message_length_position = 0
Present_DMA_count = 0
Isochronous_packetsize_memory_address = pointer to the address containing the following data 0x00000282; There are 2 locations at consecutive word boundaries having the same value;


    Please could you let me know following?
    1. The DMA transfer for a burst of 642 bytes will begin after teh corresponding bit in USBDMARSt is set (FRAME 1ms trigger). Will the second transfer soon follow this transfer or will the second burst trasfer take place only after the bit in the USBDMARSt register is set again (FRAME 1ms trigger)?
    2. If the first DMA transfer to the EP RAM has completed but hasn't been read by the host through an in transaction, will the next DMA transfer over-write the data transferred during the first burst?
    3. If the Host is in the process of reading the data from the IN Isochronous EP, and the 2nd DMA burst is initiated will the data being transfer to the host get corrupted?

    Please see the following post. The message is too long to be completed in a single post.
    Thanks very much

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