Hello, I have an 8051 custom processor, this have a memory mapped like this: 16 banks of eeprom external memory of 32kB each one. The page 0 is mapped: 0x0000-0x7FFF. The other ones: 0x8000-0xFFFF. The page number is selected via a PAGE_REG. Also I have a block of extended ram which is mapped from 0x1000-0x1FFF. And I have two RAMs more: internal ram (indirect and direct address), and external ram, of 256B amount (from 0x00 to 0xFF). Memory access from C, I do this: For eeprom:
//... select mem_page ... unsigned char pdata *ptr; ptr = address; *ptr = dat;
For extended ram:
unsigned char xdata *ptr; ptr = address // 0x1000 <= address <= 0x1FFF *ptr= dat;
For internal ram:
unsigned char idata *ptr; ptr = address; *ptr = dat;
The extended ram, and internal ram works, but the eeprom access doesn't. Someone can guide me? Thanks a lot.
g.
"the EEPROM (unless there is a language thing here) is serial"
EEPROM need not be serial. EEPROM is basically the same thing as flash memory - it's just a question of how fast you can erase the memory.
EEPROM need not be serial. EEPROM is basically the same thing as flash memory - it's just a question of how fast you can erase the memory. this is exactly why I asked. most people call serial flash devices EEPROM and parallel EEPROMs Flash
Erik
I'm not sure that's true any more - it is quite common nowadays to refer to Flash as EEPROM.
After all, "EEPROM" just stands for Electrically-Eraseable PROM - which is a perfectly valid description of Flash (as distinct from UV-EPROM).
Yes. The name flash just means an EEPROM that has been improved to allow quick-erase of large sections of the memory in constant time, while a normal EEPROM either erases cell-for-cell or have a large number of very small sectors that are erased one-by-one.
Some microprocessors have EEPROM that allows direct writes as if RAM. For external chips, you often have situations where you can perform direct writs as if RAM, but an additional interface to check if chip is ready for more writes. Sometimes, the writes are just cached in a small RAM buffer hidden within the EEPROM, and a special command is used to force the write of this sector.