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LPC 3250 Timer 0 interrupt

I am trying to test the timer for LPC3250.I am not sure what is issue with the below code.Interrupt is getting enabled but it is getting in one after another interrupt because of which it is just stuck in ISR.I tired using the CDL and it also gives the same error.
Please let me know if i am missing any setting.
/* Timer example */
void time_task()
{ /*Init timer */
// int x =0; //term_dat_out(sendstr, sizeof(sendstr));

TIMCLK_CTRL1 |= 0x04;

T0TCR =0;

T0TCR =0;

T0CTCR =00;

T0MCR =0;
T0CCR =0;
T0EMR=00;
T0TC=0;
T0PC=0;
T0PR=0;
T0MR0 = 0;
T0MR1 = 0;
T0MR2 = 0;
T0MR3 = 0;
T0IR |= 0x01;

/* Set up timer scale*/

//T0PR = timer_usec_to_val(CLKPWR_TIMER0_CLK, 100);

T0PR = 0x514;
/* match count value of 1000*/
T0MR0=999;
T0MCR |= 0x03;/* Interrupt, Reset and NO stop */
T0IR |= 0x01; /* clear the interrupt bit*/

/* Enable timers (starts counting) */ msecs = 0;

T0TCR |= 0x01; /* enable Timer*/

ctl_set_isr(Timer0_INT, 3, CTL_ISR_TRIGGER_HIGH_LEVEL, timer0_user_interrupt, 0); ctl_unmask_isr(Timer0_INT);

}

static void timer0_user_interrupt()
{ /* Clear latched timer interrupt */ //timer_ioctl(timer0dev, TMR_CLEAR_INTS, TIMER_CNTR_MTCH_BIT(0));

/* Turn on LED1 */ //ctl_board_set_leds(1); T0IR |= 0x01; /* clear the interrupt bit*/ msecs += 100;

}

  • Can you please post your code between < pre> < /pre> tags?
    It would be more readable.
    Now all I can see is that you have too much code in comments...

  • Sounds like you never acknowledge your interrupt. Have a look in the user manual/sample code.

  • Thanks for the reply.Here is the code without commented line.
    I am posting two version of code.In both cases I am facing the same issue.
    1. Without CDL provided by NXP.
    =================================================
    void timer0_user_interrupt(void)
    { /* Clear latched timer interrupt */ timer_ioctl(timer0dev, TMR_CLEAR_INTS, TIMER_CNTR_MTCH_BIT(0));

    msecs += 100;

    }
    ================================================================
    /* Timer example */
    void time_task()
    { /*Init timer */

    TIMCLK_CTRL1 |= 0x04; /* Power cntrl reg for T0*/

    T0TCR =0;
    T0CTCR =00;
    T0MCR =0;
    T0CCR =0;
    T0EMR=00;
    T0TC=0;
    T0PC=0;
    T0PR=0;
    T0MR0 = 0;
    T0MR1 = 0;
    T0MR2 = 0;
    T0MR3 = 0;
    T0IR |= 0x01;

    /* Set up timer scale*/

    T0PR = 0x514;
    /* match count value of 1000*/
    T0MR0=999;
    T0MCR |= 0x03;/* Interrupt, Reset and NO stop */
    T0IR |= 0x01; /* clear the interrupt bit*/

    /* Enable timers (starts counting) */ msecs = 0;

    T0TCR |= 0x01; /* enable Timer*/

    ctl_set_isr(Timer0_INT, 3, CTL_ISR_TRIGGER_HIGH_LEVEL, timer0_user_interrupt, 0); ctl_unmask_isr(Timer0_INT);

    }

    =====================================================
    2. code with CDL

    /* Timer example */
    void time_task()
    { /*Init timer */

    TMR_PSCALE_SETUP_T pscale; TMR_MATCH_SETUP_T msetup;

    /* Open timers - this will enable the clocks for all timers when match control, match output, and capture control functions disabled. Default clock will be internal. */ timer0dev = timer_open(TIMER_CNTR0, 0); timer_ioctl(timer0dev, TMR_ENABLE, 0); /******************************************************************/ /* Setup timer 0 for a 10Hz match rate */

    /* Use a prescale count time of 100uS */ pscale.ps_tick_val = 0; /* Use ps_us_val value */ pscale.ps_us_val = 100; /* 100uS */ timer_ioctl(timer0dev, TMR_SETUP_PSCALE, (INT_32) &pscale);

    /* Use a match count value of 1000 (1000 * 100uS = 100mS (10Hz)) */ msetup.timer_num = 0; /* Use match register set 0 (of 0..3) */ msetup.use_match_int = TRUE; /* Generate match interrupt on match */ msetup.stop_on_match = FALSE; /* Do not stop timer on match */ msetup.reset_on_match = TRUE; /* Reset timer counter on match */ msetup.match_tick_val = 999; /* Match is when timer count is 1000 */ timer_ioctl(timer0dev, TMR_SETUP_MATCH, (INT_32) &msetup);

    /* Clear any latched timer 0 interrupts and enable match interrupt */ timer_ioctl(timer0dev, TMR_CLEAR_INTS, (TIMER_CNTR_MTCH_BIT(0) | TIMER_CNTR_MTCH_BIT(1) | TIMER_CNTR_MTCH_BIT(2) | TIMER_CNTR_MTCH_BIT(3) | TIMER_CNTR_CAPT_BIT(0) | TIMER_CNTR_CAPT_BIT(1) | TIMER_CNTR_CAPT_BIT(2) | TIMER_CNTR_CAPT_BIT(3))); /******************************************************************/ /* Enable timers (starts counting) */ msecs = 0; timer_ioctl(timer0dev, TMR_ENABLE, 1); ctl_set_isr(Timer0_INT, 3, CTL_ISR_TRIGGER_HIGH_LEVEL, timer0_user_interrupt, 0); ctl_unmask_isr(Timer0_INT);

    }

  • HI Tamir,
    Sorry looks like i am missing your point here.Please elaborate.
    ISR is executed in this routine
    void timer0_user_interrupt(void)
    { /* Clear latched timer interrupt */

    timer_ioctl(timer0dev, TMR_CLEAR_INTS, TIMER_CNTR_MTCH_BIT(0)); /* Turn on LED1 */

    msecs += 100;

    }