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Further in the series of dumb questions I am too embarrased to identify myself as having publicly asked, is the following:
Should my boiler plate bit-banger I2C C code be able to be temporarily interrupted by other tasks at any point during communication?
Does the I2C standard permit brief pauses in bus activity, whilst the processor attends to more pressing duties?
Boz.
"Does the I2C standard permit brief pauses in bus activity, whilst the processor attends to more pressing duties?"
Generally yes, although in a multi-master environment, I would try to prevent interruption while SCL is high. If you allow pauses in the middle of a transaction, it's best to do so while SCL is low.
If using other I2C-bus protocols like SMBus for example, bus timing is important. SMBus devices could time out if the bus is not running fast enough or SCL is held low too long.