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I have a large project that was designed before my time. I seem to have random, glitchy problems that are hard to track down.
I think the problem lies in my ram. Lots of vars are stored in the (xdata) ram according to my MAP file. Looking at the attached schematic snippet www.freeimagehosting.net/.../58ce2f8b56.jpg, it appears the RAM is selected when A15 is 0 (due to some nand gates). So this means my valid RAM addresses are 0x0 - 0x8000... correct?
U27 is my ram. LRAMCS/LRAMCSO is the chip sel for the RAM. LA15 is A15 from the uP. LRAMCS is active when A15 and PSEN are 0.
In some cases when playing around with compiler/linker settings, I noticed, even though the amount of xdata usage was less than 0x8000, i had xdata addressed at locations higher than 0x8000. Does the linker not use the memory sequentially? Since then, I defined my ram in the linker and I dont think this problem has occured since. Unfortunately, I havent had time to test if this fixes the operational problems.
Any tips to help track down my problem?
Thanks all your valuable insight!
Hi Chris,
I see that u r working on C51.Can you help me with assembly language coding that can be done in this?? reply asap.